SCOPUS 정보 검색 플랫폼

Electrical Overstress/Electrostatic Discharge Symposium Proceedings

Volumn 2001-January, Issue , 2001, Pages 203-213

Evaluation of diode-based and NMOS/Lnpn-based ESD protection strategies in a triple gate oxide thickness 0.13 μm CMOS logic technology

(7) Gauthier, Robert a Stadler, Wolfgang b Esmark, Kai b Riess, Philipp b Salman, Akram c Muhammad, Mujahid a Putnam, Chris a

a IBM MICROELECTRONICS (United States)

b INFINEON TECHNOLOGIES AG (Germany)

c GEORGE MASON UNIVERSITY (United States)

Author keywords

Biological system modeling; CMOS logic circuits; CMOS technology; Electrostatic discharge; Microelectronics; MOS devices; Protection; Research and development; Robustness; Semiconductor diodes

Indexed keywords

BIOLOGICAL SYSTEMS; CMOS INTEGRATED CIRCUITS; ELECTROSTATIC DEVICES; ELECTROSTATIC DISCHARGE; LOGIC CIRCUITS; MICROELECTRONICS; MOS DEVICES; ROBUSTNESS (CONTROL SYSTEMS); SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR DEVICES;

BIOLOGICAL SYSTEM MODELING; CMOS LOGIC CIRCUITS; CMOS TECHNOLOGY; PROTECTION; RESEARCH AND DEVELOPMENT;

SEMICONDUCTOR DIODES;

EID: 84883070328 PISSN: 07395159 EISSN: None Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper

Times cited : (13)

References (12)

1
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2
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3
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4
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5
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- Stadler, W.¹ Guggenmos, X.² Egger, P.³ Gieser, H.⁴ Musshoff, C.⁵

6
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- Barth, J.¹ Richner, J.² Verhaege, K.³

7
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- A. Salman, R.Gauthier, W.Stadler, K. Esmark, M. Muhammad, C.Putnam, Proc IRPS Symp. 2001, p. 219
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- Salman, A.¹ Gauthier, R.² Stadler, W.³ Esmark, K.⁴ Muhammad, M.⁵ Putnam, C.⁶

8
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9
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- Litzenberger, M.¹ Pichler, R.² Pogany, D.³ Gornik, E.⁴ Esmark, K.⁵ Goßner, H.⁶

10
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11
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12
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- PhD thesis Zurich
- K. Esmark, PhD thesis, Swiss Federal Institute of Technology, Zurich, 2001
- (2001) Swiss Federal Institute of Technology
- Esmark, K.¹

* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.