Implementation of a comprehensive and robust MOSFET model in cadence SPICE for ESD applications

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 21, Issue 12, 2002, Pages 1497-1502

  Gao, X F ^a   Liou, J J ^a   Bernier, J ^b   Croft, G ^b   Ortiz Conde, A ^c  

^a University of Central Florida   (United States)

^b INTERSIL CORPORATION   (United States)

^c UNIVERSIDAD SIMÓN BOLÍVAR   (Venezuela)

Author keywords

Electrostatic discharge; Modeling; MOSFET; SPICE

Indexed keywords

COMPUTER SIMULATION; ELECTRIC DISCHARGES; ELECTROSTATICS; MICROPROCESSOR CHIPS; MOSFET DEVICES;

ELECTROSTATIC DISCHARGES (ESD);

COMPUTER AIDED DESIGN;

EID: 0036908623     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2002.804379     Document Type: Article

References (21)

1. J. Vinson and J.J. Liou, "Electrostatic discharge in semiconductor devices: An overview," IEEE Proc., vol. 86, pp. 399-418, Feb. 1998.
2. _, "Electrostatic discharge in semiconductor devices: Protection techniques," IEEE Proc., vol. 88, pp. 1878-1900, Dec. 2000.
3. F.C. Hsu, P.K. Ko, S. Tam, C. Hu, and R. Muller, "An analytical break-down model for short-channel MOSFET's," IEEE Trans. Electron. Devices, vol. ED-29, pp. 1735-1740, 1982.
4. N.D. Jankovic, "Pre-turn-on source bipolar injection in graded NMOST's," IEEE Trans. Electron. Devices, vol. 38, pp. 2527-2530, Nov. 1991.
5. A. Amerasekera, S. Ramaswamy, M.-C. Chang, and C. Duvvury, "Modeling MOS snapback and parasitic bipolar action for circuit-level ESD and high current simulations," in Int. Reliability Physics Symp., 1996, pp. 318-326.
6. X.F. Gao, J.J. Liou, A. Ortiz-Conde, J. Bernier, and G. Croft, "A physics-based model for the substrate resistance of MOSFET's," Solid-State Electron., vol. 46, pp. 853-857, June 2002.
7. A. Amerasekera, S. Ramaswary, M. Chang, and C. Duvvury, "Modeling MOS snapback and parasitic bipolar action for circuit-level ESD and high current simulations," in Proc. 34th Annu. IEEE Int. Reliability Physics, 1996, pp. 318-326.
8. S.L. Lim, X.Y. Zhang, Z. Yu, S. Beebe, and R.W. Dutton, "A computationally stable quasiempirical compact model for the simulation of MOS breakdown in ESD-protection circuit design," in Proc. Int. Conf. Simulation Semiconductor Processes and Devices, 1997, pp. 161-164.
9. V. Gupta, A. Amerasekera, S. Ramaswamy, and A. Tsao, "ESD-related process effects in mixed-voltage sub-0.5 μm technologies," in Proc. EOS/ESD Symp., 1998, pp. 161-169.
10. X.F. Gao, J.J. Liou, J. Bernier, and G. Croft, "An improved model for the substrate current of submicron MOSFET's," Solid-State Electron., vol. 46, pp. 1395-1398, Sept, 2002.
11. H. Wong and M.C. Pooh, "Approximation of the length of velocity saturation region in MOSFET's," IEEE Trans. Electron. Devices, vol. 44, 1997.
12. BSIM3v3.22 Manual, Univ. California, Berkley, 1996.
13. "Microcal Origin 5.0," Microcal Software Inc., 1997.
14. Affirma Spectra Circuit Simulator Device Model Equation, Cadence Manual, 1999.
15. D. MacSweeney, K.G. McCarthy, A. Mathewson, and B. Mason, "A spice compatible subcircuit model for lateral bipolar transistor in a CMOS process," IEEE Trines. Electron. Devices, vol. 45, Sept. 1998.
16. A. Amerasekera and C. Duvvury, ESD in Silicon Integrated Circuits. London, U.K.: Wiley-Chichester, 1995.
17. R.W. Dutton, "Bipolar transistor modeling of avalanche generation for computer circuit simulation," IEEE Trans. Electron. Devices, vol. ED-22, pp. 334-338, June 1975.
18. F.C. Hsu, P.K. Ko, S. Tan, C.M. Hu, and R.S. Muller, "An analytical breakdown model for short-channel MOSFET's," IEEE Trans. Electron. Devices, vol. ED-29, Nov. 1982.
19. M. Pinto-Guedes and P.C. Chan, "A circuit simulation model for bipolar-induced breakdown in MOSFET," IEEE Trans. Computer-Aided Design, vol. 7, pp. 289-294, Feb. 1988.
20. SPECTRA Manual, 1999.
21. Smart SPICE C-Interpreter User's Manual, 2000.