GGSCRs: GGNMOS Triggered silicon controlled rectifiers for ESD protection in deep sub-micron CMOS processes

Electrical Overstress/Electrostatic Discharge Symposium Proceedings

Volumn 2001-January, Issue , 2001, Pages 22-31

  Russ, Christian C ^a   Mergens, Markus P J ^a   Verhaege, Koen G ^b   Armer, John ^a   Jozwiak, Phillip C ^a   Kolluri, Girija ^a   Avery, Leslie R ^a  

^a SARNOFF CORPORATION   (United States)

^b Sarnoff Europe   (Belgium)

Author keywords

Breakdown voltage; CMOS process; CMOS technology; Electrostatic discharge; Europe; Integrated circuit testing; Low voltage; MOS devices; Protection; Thyristors

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC BREAKDOWN; ELECTRONIC EQUIPMENT TESTING; ELECTROSTATIC DISCHARGE; INTEGRATED CIRCUIT TESTING; MOS DEVICES; THYRISTORS;

CMOS PROCESSS; CMOS TECHNOLOGY; EUROPE; LOW VOLTAGES; PROTECTION;

ELECTROSTATIC DEVICES;

EID: 84948982831     PISSN: 07395159     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)

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10. H. Wolf, H. Gieser, W. Wilkening, Analyzing the Switching Behavior of ESD-Protection Transistors by Very Fast Transmission Line Pulsing, EOS/ESD 1999, pp. 28
11. K. Verhaege, C. Russ, Wafer Cost Reduction through Design of High Performance Fully Silicided ESD Devices, EOS/ESD 2000, pp. 287