Substrate noise coupling in SoC design: Modeling, avoidance, and validation

Proceedings of the IEEE

Volumn 94, Issue 12, 2006, Pages 2109-2137

  Afz Kusha, Ali ^a,b   Nagata, Makoto ^a,c   Verghese, Nishath K ^a,d   Allstot, David J ^a,e  

^a IEEE   (Iran)

^b UNIVERSITY OF TEHRAN   (Iran)

^c KOBE UNIVERSITY   (Japan)

^d Clear Shape Technologies   (United States)

^e University of Washington   (United States)

Author keywords

Boundary element methods; Digital switching noise; Finite difference methods; Integrated circuit noise; Mixed analog digital integrated circuits; Network reduction methods; Noise; Noise generators; Signal integrity; Substrate coupling

Indexed keywords

BOUNDARY ELEMENT METHOD; COMPUTER SIMULATION; FINITE DIFFERENCE METHOD; NOISE GENERATORS; PARAMETER ESTIMATION;

DIGITAL SWITCHING NOISE; INTEGRATED CIRCUIT NOISE; MIXED ANALOG-DIGITAL INTEGRATED CIRCUITS; NETWORK REDUCTION METHODS; SIGNAL INTEGRITY; SUBSTRATE COUPLING;

INTEGRATED CIRCUIT LAYOUT;

EID: 33947389668     PISSN: 00189219     EISSN: None     Source Type: Journal    
DOI: 10.1109/JPROC.2006.886029     Document Type: Review

References (130)

1. T. Kadoyama, N. Suzuki, N. Sasho, H. Iizuka, I. Nagase, H. Usukubo, and M. Katakura, "A complete single-chip GPS receiver with 1.6-V 24-mW radio in 0.18- μm CMOS," IEEE J. Solid-Slate Circuits, vol. 39, no. 4, pp. 562-568, Apr. 2004.
2. D. R. Pehlke, A. Burstein, and M. F. Chang, "Extremely high-Q tunable inductor for Si-based RF integrated circuit applications," in Proc. IEEE Int. Electron Devices Meeting, 1997, pp. 63-66.
3. J. A. Olmstead and S. Vulih, "Noise problems in mixed analog-digital integrated circuits," in Proc. IEEE Custom Integrated Circuits Conf., 1987, pp. 659-662.
4. S. Masui, "Simulation of substrate coupling in mixed-signal MOS circuits," in Proc. Symp. VLSI Circuits, 1992, pp. 42-43.
5. S. Kiaei, D. J. Allstot, K. Hansen, and N. K. Verghese, "Noise considerations for mixed-signal RF IC transceivers," ACM J. Wireless Networks, vol. 4, pp. 41-53, Jan. 1998.
6. N. K. Verghese and D. J. Allstot, "Computer-aided design considerations for mixed-signal coupling in RF integrated circuits," IEEE J. Solid-State Circuits, vol. 33, no. 3, pp. 314-323, Mar. 1998.
7. B. R. Stanisic, N. K. Verghese, R. A. Rutenbar, L. R. Carley, and D. J. Allstot, "Addressing substrate coupling in mixed-mode ICs: Simulation and power distribution systems," IEEE J. Solid-State Circuits, vol. 29, no. 3, pp. 226-238, Mar. 1994.
8. T. Tsukada and K. Makie-Fukuda, "Approaches to reducing digital-noise coupling in CMOS mixed-signal LSIs," IEICE Trans. Fundamentals of Electronics, Communications Computer Sciences, vol. E80-A, pp. 263-275, Feb. 1997.
9. E. Charbon, R. Gharpurey, R. G. Meyer, and A. Sangiovanni-Vincentelli, "Substrate optimization based on semi-analytical techniques," IEEE Trans. Computer-Aided Design Integrated Circuits Syst., vol. 18, no. 2, pp. 172-190, Feb. 1999.
10. M. Nagata, J. Nagai, T. Morie, and A. Iwata, "Measurements and analyses of substrate noise waveform in mixed-signal IC environment," IEEE Trans. Computer-Aided Design Integrated Circuits Syst., vol. 19, no. 6, pp. 671-678, Jun. 2000.
11. D. K. Su, M. J. Loinaz, S. Masui, and B. A. Wooley, "Experimental results and modeling techniques for substrate noise in mixed-signal integrated circuits," IEEE J. Solid-State Circuits, vol. 28, no. 4, pp. 420-430, Apr. 1993.
12. R. B. Merrill, W. M. Young, and K. Brehmer, "Effect of substrate material on crosstalk in mixed analog/digital integrated circuit," in Proc. IEEE Int. Electron Devices Meeting, 1994, pp. 433-436.
13. X. Aragones and A. Rubio, "Experimental comparison of substrate noise coupling using different wafer types," IEEE J. Solid-State Circuits, vol. 34, no. 10, pp. 1405-1409, Oct. 1999.
14. J. Briaire and S. Krisch, "Principles of substrate crosstalk generation in CMOS circuits," IEEE Trans. Computer-Aided Design Integrated Circuits Syst., vol. 19, no. 6, pp. 645-653, Jun. 2000.
15. S. Mitra, R. A. Rutenbar, L. R. Carley, and D. J. Allstot, "A methodology for rapid estimation of substrate-coupled switching noise," in Proc. IEEE Custom Integrated Circuits Conf., 1995, pp. 129-132.
16. M. Nagata and A. Iwata, "Substrate noise simulation techniques for analog-digital mixed LSI design," IEICE Trans. Fund. Electronics, Communications Computer Sciences, vol. E82-A, pp. 271-278, Feb. 1999.
17. _, "Substrate crosstalk analysis in mixed signal CMOS integrated circuits," in Proc. IEEE Asia South Pacific Design Automation Conf., 2000, pp. 623-629.
18. N. K. Verghese, T. J. Schmerbeck, and D. J. Allstot, Simulation Techniques and Solutions for Mixed-signal Coupling in Integrated Circuits. Boston, MA: Kluwer, 1995.
19. M. Nagata, T. Ohmoto, Y. Murasaka, T. Morie, and A. Iwata, "Effects of power-supply parasitic components on substrate noise generation in large-scale digital circuits," in Proc. Symp. VLSI Circuits, 2001, pp. 159-162.
20. A. J. Rainal, "Eliminating inductive noise of external chip interconnections," IEEE J. Solid-State Circuits, vol. 29, no. 2, pp. 126-129, Feb. 1994.
21. J. M. Casalta, X. Aragones, and A. Rubio, "Substrate coupling evaluation in BiCMOS technology," IEEE J. Solid-State Circuits, vol. 32, no. 4, pp. 598-603, Apr. 1997.
22. X. Aragones, F. Moll, M. Roca, and A. Rubio, "Analysis and modeling of parasitic substrate coupling in CMOS circuits," IEE Proc. Circuits, Devices Systems, vol. 142, pp. 307-312, Oct. 1995.
23. K. Joardar, "A simple approach to modeling cross-talk in integrated circuits," IEEE J. Solid-State Circuits, vol. 29, no. 10, pp. 1212-1219, Oct. 1994.
24. N. K. Verghese, D. J. Allstot, and M. A. Wolfe, "Verification techniques for substrate coupling and their application to mixed-signal IC design," IEEE J. Solid-State Circuits, vol. 31, no. 3, pp. 354-365, Mar. 1996.
25. J. Catrysse, "Measured distortion of the output-waveform of an integrated OPAMP due to substrate noise," IEEE Trans. Electromagnetic Compatibility, vol. 37, no. 5, pp. 310-312, May 1995.
26. T. Blalack and B. A. Wooley, "The effects of switching noise on an oversampling A/D converter," in Proc. IEEE Int. Solid-State Circuits Conf., 1995, pp. 200-201, 367.
27. A. Gothenberg, E. Soenen, and H. Tenhunen, "Modeling and analysis of substrate coupled noise in pipelined data converters," in Proc. Southwest Symp. Mixed-Signal Design, 2000, pp. 125-130.
28. H. H. Y. Chan and Z. Zilic, "Estimating phase-locked loop jitter due to substrate coupling: A cyclostationary approach," in Proc. Int. Symp. Quality Electronic Design, 2004, pp. 309-314.
29. P. Heydari, "Analysis of the PLL jitter due to power/ground and substrate noise," IEEE Trans. Circuits Syst. I: Regular Papers, vol. 51, no. 12, pp. 2404-2416, Dec. 2004.
30. _, "Characterizing the effects of the PLL jitter due to substrate noise in discrete-time delta-sigma modulators," IEEE Trans. Circuits Syst. I: Regular Papers, vol. 52, no. 6, pp. 1073-1085, Jun. 2005.
31. P. Larsson, "Measurements and analysis of PLL jitter caused by digital switching noise," IEEE J. Solid-State Circuits, vol. 36, no. 7, pp. 1113-1119, Jul. 2001.
32. R. J. Welch and A. T. Yang, "Substrate coupling analysis and simulation for an industrial phase-locked loop," in IEEE Int. Symp. Circuits Syst., 1998, pp. 94-97.
33. G. Van der Plas, C. Soens, M. Badaroglu, P. Wambacq, and S. Donnay, "Modeling and experimental verification of substrate coupling and isolation techniques in mixed-signal ICs on a lightly-doped substrate," in Proc. Symp. VLSI Circuits, 2005, pp. 280-283.
34. A. Pun, T. Yeung, J. Lau, F. J. R. Clement, and D. K. Su, "Substrate noise coupling through planar spiral inductor," IEEE J. Solid-State Circuits, vol. 33, no. 6, pp. 877-884, Jun. 1998.
35. Z. Zhang, A. Pun, and J. Lau, "Interference issues in silicon RFIC design," in Proc. IEEE Radio Frequency Integrated Circuits Symp., 1998. pp. 119-122.
36. M. Xu, D. K. Su, D. K. Shaeffer, T. H. Lee, and B. A. Wooley, "Measuring and modeling the effects of substrate noise on the LNA for a CMOS GPS receiver," IEEE J. Solid-State Circuits, vol. 36, no. 3, pp. 473-485, Mar. 2001.
37. R. Gharpurey, "A methodology for measurement and characterization of substrate noise in high frequency circuits," in Proc. IEEE Custom Integrated Circuits Conf., 1999. pp. 487-490.
38. S. Hazenboom, T. S. Fiez, and K. Mayaram, "A comparison of substrate noise coupling in lightly and heavily doped CMOS processes for 2.4-GHz LNAs," IEEE J. Solid-State Circuits, vol. 41, no. 3, pp. 574-587, Mar. 2006.
39. C. Hu, VLSI Electronics: Alicrostructure Science. New York: Academic, 1981, vol. 18.
40. K. Shimazaki, H. Tsujikawa, S. Kojima, and S. Hirano, "LEMINGS: LSI's EMI-noise analysis with gate level simulator," in Proc. Int. Symp. Quality Electronic Design, 2000, pp. 129-136.
41. E. Charbon, P. Miliozzi, L. Carloni, A. Ferrari, and A. Sangiovanni-Vincentelli, "Modeling digital substrate noise injection in mixed-signal IC's," IEEE Trans. Computer-Aided Design Integrated Circuits Syst., vol. 18, no. 3, pp. 301-310, Mar. 1999.
42. P. Miliozzi, L. Carloni, E. Charbon, and A. Sangiovanni-Vincentelli, "SUBWAVE: A methodology for modeling digital substrate noise injection in mixed-signal ICs," in Proc. IEEE Custom Integrated Circuits Conf., 1996, pp. 385-388.
43. M. van Heijningen, M. Badaroglu, S. Donnay, M. Engels, and I. Bolsens, "High-level simulation of substrate noise generation including power supply noise coupling," in Design Automation Conf., 2000, pp. 446-451.
44. M. Nagata, T. Morie, and A. Iwata, "Modeling substrate noise generation in CMOS digital integrated circuits," in Proc. IEEE Custom Integrated Circuits Conf., 2002, pp. 501-504.
45. K. J. Kerns, I. L. Wemple, and A. T. Yang, "Stable and efficient reduction of substrate model networks using congruence transforms," in Proc. IEEE/ACM Int. Conf. Computer-Aided Design, 1995, pp. 207-214.
46. N. K. Verghese, D. J. Allstot, and S. Masui, "Rapid simulation of substrate coupling effects in mixed-mode ICs," in Proc. IEEE Custom Integrated Circuits Conf., 1993, pp. 18.3.1-18.3.4.
47. S. Kumashiro, R. A. Rohrer, and A. J. Strojwas, "A new efficient method for the transient simulation of three-dimensional interconnect structures," in Proc. IEEE Int. Electron Devices Meeting, 1990, pp. 193-196.
48. F. J. R. Clement, E. Zysman, M. Kayal, and M. Declercq; "LAYIN: Toward a global solution for parasitic coupling modeling and visualization," in Proc. IEEE Custom Integrated Circuits Conf., 1994, pp. 537-540.
49. T. Smedes, "Substrate resistance extraction for physics-based layout verification," in Proc. IEEE/PRORISC Workshop Circuits Systems Signal Processing, 1993, pp. 101-106.
50. J. P. Costa, M. Chou, and L. M. Silveria, "Efficient techniques for accurate modeling and simulation of substrate coupling in mixed-signal IC's," IEEE Trans. Computer-Aided Design Integrated Circuits Syst., vol. 18, no. 5, pp. 597-607, May 1999.
51. M. Chou and J. White, "Multilevel integral equation methods for the extraction of substrate coupling parameters in mixed-signal IC's," in Design Automation Conf., 1998, pp. 20-25.
52. N. K. Verghese, D. J. Allstot, and M. A. Wolfe, "Fast parasitic extraction for substrate coupling in mixed-signal ICs," in Proc. IEEE Custom Integrated Circuits Conf., 1995, pp. 121-124.
53. J. D. Jackson, Classical Electrodynamics. New York: Wiley, 1962.
54. R. Gharpurey and R. G. Meyer, "Modeling and analysis of substrate coupling in integrated circuits," in Proc. IEEE Custom Integrated Circuits Conf., 1995, pp. 125-128.
55. A. M. Niknejad, R. Gharpurey, and R. G. Meyer, "Numerically stable Green's function for modeling and analysis of substrate coupling in integrated circuits," IEEE Trans. Computer-Aided Design Integrated Circuits Syst., vol. 17, no. 4, pp. 305-315, Apr. 1998.
56. J. P. Costa, M. Chou, and K. M. Silveira, "Efficient techniques for accurate extraction and modeling of substrate coupling in mixed-signal IC's," in Proc. Design, Automation Test Eur. Conf., 1999, pp. 396-400.
57. J. Kanapka, J. Phillips, and J. White, "Fast methods for extraction and sparsification of substrate coupling," in Proc. ACM/IEEE Design Automation Conf., 2000, pp. 738-743.
58. Z. Ye, W. Yu, and Z. Yu, "Efficient 3-D capacitance extraction considering lossy substrate with multilayered Green's function," IEEE Trans. Microwave Theory Techniques, vol. 54, no. 5, pp. 2128-2137, May 2006.
59. C. Xu, T. Fiez, and K. Mayaram, "On the numerical stability of Green's function for substrate coupling in integrated circuits," IEEE Trans. Computer-Aided Design Integrated Circuits Syst., vol. 24, pp. 653-658, Apr. 2005.
60. _, "An efficient formulation for substrate parasitic extraction accounting for nonuniform current distribution," IEEE Trans. Circuits Syst. I: Regular Papers, vol. 51, no. 6, pp. 1223-1233, Jun. 2004.
61. X. Wang, \V. Yu, and Z. Wang, "Substrate resistance extraction with direct boundary element method," in Proc. Asia South Pacific Design Automation Conf., 2005, pp. 208-211.
62. E. Schrik and N. R. van der Meijs, "Combined BEM/FEM substrate resistance modeling," in Proc. Design Automation Conf., 2002, pp. 771-776.
63. J. M. S. Silva and L. M. Silveira, "Multigrid-based substrate coupling model extraction," in Proc. IEEE Int. Symp. Circuits Systems, 2004, pp. 169-173.
64. P. Maffezzoni, "Analysis of substrate coupling by means of a stochastic method," IEEE Electron Device Lett., vol. 23, no. 6, pp. 351-353, Jun. 2002.
65. D. A. White and M. Stowell, "Full-wave simulation of electromagnetic coupling effects in RF and mixed-signal ICs using a time-domain finite-element method," IEEE Trans. Microwave Theory Techniques, vol. 52, no. 5, pp. 1404-1413, May 2004.
66. S. Hsu, T. S. Fiez, and K. Mayaram, "Modeling of substrate noise coupling for nMOS transistors in heavily doped substrates," IEEE Trans. Electron Devices, vol. 52, no. 8, pp. 1880-1886, Aug. 2005.
67. H. Lan, T. W. Chen, C. O. Chui, P. Nikaeen, J. W. Kim, and R. W. Dutton, "Synthesized compact model and experimental results for substrate noise coupling in lightly doped processes," in Proc. IEEE Custom Integrated Circuits Conf., 2005, pp. 469-472.
68. N. Masoumi, M. I. Elmasry, S. Safavi-Naeini, and L. Hadi, "A novel analytical model for evaluation of substrate crosstalk in VLSI circuits," in Proc. Eirst IEEE Int. Workshop Electronic Design, Test Applicat., 2002, pp. 355-359.
69. S. Ponnapalli, N. Verghese, W. K. Chu, and G. Coram, "Preventing a noisequake," IEEE Circuits Devices Mag., vol. 17, pp. 19-28, Nov. 2001.
70. M. Nagata and A. Iwata, "A macroscopic substrate noise model for full chip mixed-signal design verification," in Proc. Symp. VLSI Circuits, 1997, pp. 37-38.
71. M. K. Mayes and S. W. Chin, "All Verilog mixed-signal simulator with analog behavioral and noise models," in Proc. Symp. VLSI Circuits, 1996, pp. 186-187.
72. J. Lundgren, T. Ytterdal, K. Vonbun, and M. O'Nils, "Taking mixed-signal substrate noise coupling simulation to the behavioral level using SystemC," in Proc. IEEE Int. Workshop System-on-Chip for Real-Time Applications, 2004, pp. 201-205.
73. A. Doboli and R. Vemuri, "Fast evaluation of digital switching noise for synthesis of mixed-signal applications," in Proc. IEEE Int. Workshop Behavioral Modeling Simulation, 2001, pp. 32-37.
74. M. Badaroglu, G. Van der Plas, P. Wambacq, S. Donnay, G. G. E. Gielen, and H. J. De Man, "SWAN: High-level simulation methodology for digital substrate noise generation," IEEE Trans. Very Large Scale Integration (VLSI) Syst., vol. 14, no. 1, pp. 23-33, Jan. 2006.
75. L. Li, Z. Li, and H. Tenhunen, "A simple macromodeling approach for analyzing substrate coupling in an RF mixer IC," in Proc. Int. Conf. ASIC, 2003, pp. 1029-1032.
76. M. van Heijningen, M. Badaroglu, S. Donnay, G. G. E. Gielen, and H. J. De Man, "Substrate noise generation in complex digital systems: Efficient modeling and simulation methodology and experimental verification," IEEE J. Solid-State Circuits, vol. 37, no. 8, pp. 1065-1072, Aug. 2002.
77. A. Koukab, K. Banerjce, and M., Declercq, "Modeling techniques and verification methodologies for substrate coupling effects in mixed-signal system-on-chip designs," IEEE Trans. Computer-Aided Design Integrated Circuits Syst., vol. 23, no. 6, pp. 823-836, Jun. 2004.
78. H. M. Habal, T. S. Fiez, and K. Mayaram, "An accurate and efficient estimation of switching noise in synchronous digital circuits," in Proc. IEEE Int. Symp. Circuits Systems, 2004, pp. 485-488.
79. R. C. Melville, P. Feldmann, and J. Roychowdhury, "Efficient multi-tone distortion analysis of analog integrated circuits," in Proc. IEEE Custom Integrated Circuits Conf., 1995, pp. 241-244.
80. A. R. Telichevesky, K. Kunden, and J. White, "Efficient steady-state analysis based on matrix-free Krylov-subspace methods," in Proc. Design Automation Conf., 1995, pp. 480-484.
81. K. H. Kwan, I. L. Wemple, and A. T. Yang, "Simulation and analysis of substrate coupling in realistically-large mixed-A/D circuits," in Proc. Symp. VLSI Circuits, 1996, pp. 184-185.
82. B. R. Stanisic, R. A. Rutenbar, and L. R. Carley, "Addressing noise decoupling in mixed-signal IC's: Power distribution design and cell customization," IEEE J. Solid-State Circuits, vol. 30, no. 3, pp. 321-326, Mar. 1995.
83. S. Mitra, R. A. Rutenbar, L. R. Carley, and D. J. Allstot, "Substrate-aware mixed-signal macrocell placement in WRIGHT," IEEE J. Solid-State Circuits, vol. 30, no. 3, pp. 269-278, Mar. 1995.
84. C. Lin and D. M. W. Leenaerts, "A new efficient method for substrate-aware device-level placement," in Proc. Asia South Pacific Design Automation Conf., 2000, pp. 533-536.
85. A. Hermann, M. Olbrich, and E. Barke, "Placing substrate contacts into mixed-signal circuits controlling circuit performance," in Proc. IEEE Custom Integrated Circuits Conf., 2003. pp. 373-376.
86. T. Brandtner and R. Weigel, "SubCALM: A program for hierarchical substrate coupling simulation on floorplan level," in Proc. Design, Automation Test Eur. Conf., 2004. pp. 616-621.
87. G. Blakiewicz, M. Jeske, M. Chrzanowska-Jeske, and J. S. Zhang, "Substrate noise modeling in early floorplanning of MS-SoCs," in Proc. Asia South Pacific Design Automation Conf., 2005, pp. 819-823.
88. M. Cho, H. Shin, and D. Z. Pan, "Fast substrate noise-aware floorplanning with preference directed graph for mixed-signal SoCs," in Proc. Asia South Pacific Design Automation Conf., 2006, pp. 765-770.
89. D. J. Allstot, S. Chee, S. Kiaei, and M. Shrivastawa, "Folded source-coupled logic vs. CMOS static logic for low-noise mixed-signal ICs," IEEE Trans. Circuits Syst. I: Fund. Theory Applicat., vol. 40, no. 9, pp. 553-563, Sep. 1993.
90. S. R. Maskai, S. Kiaei, and D. J. Allstot, "Synthesis techniques for CMOS folded source-coupled logic circuits," IEEE J. Solid-State Circuits, vol. 27, no. 8, pp. 1157-1167, Aug. 1992.
91. M. Maleki and S. Kiaei, "Enhancement source-coupled logic for mixed-mode VLSI circuits," IEEE Trans. Circuits Syste. II: Analog Digital Signal-Processing, vol. 39, no. 6, pp. 399-402, Jun. 1992.
92. J. L. Gonzalez and A. Rubio, "TCMOS: Low noise power supply technique for digital ICs," Electron. Lett., vol. 31, pp. 1338-1339, Aug. 1995.
93. R. Senthinathan and J. L. Prince, "Application specific CMOS output driver circuit design techniques to reduce simultaneous switching noise," IEEE J. Solid State Circuits, vol. 28, no. 12, pp. 1383-1388, Dec. 1993.
94. A. Vittal, H. Ha, F. Brewer, and M. Marek-Sadowska, "Clock skew optimization for ground bounce control," in Proc. IEEE/ACM Int. Conf. Computer-Aided Design, 1996, pp. 395-399.
95. W.-C. D. Lam, C.-K. Koh, and C.-W. A. Tsao, "Power supply noise suppression via clock skew scheduling," in Proc. Int. Symp. Quality Electronic Design, 2002, pp. 355-360.
96. W. Groeneveld, "Groundbounce in CMOS," in Proc. Workshop Advances Analog Integrated Circuit Design, Apr. 1993.
97. M. Ingels and M. S. J. Steyaert, "Design strategies and decoupling techniques for reducing the effects of electrical interference in mixed-mode IC's," IEEE J. Solid-State Circuits, vol. 32, no. 7, pp. 1136-1141, Jul. 1997.
98. G. H. Warren and C. Jungo, "Noise, crosstalk and distortion in mixed analog/digital integrated circuits," in Proc. IEEE Custom Integrated Circuits Conf., 1988, pp. 12.1.1-12.1.4.
99. S. Marukawa and K. Dei, "An 8 bit 20 MS/s CMOS subranging A/D converter with PSRR compensation," in Proc. IEICE Spring Nat. Conf., 1990, pp. 5238.
100. B. Nauta and G. Hoogzaad, "How to deal with substrate noise in analog CMOS circuits," in Proc. Eur. Conf. Circuit Theory Design, 1997, pp. 12.1-12.6.
101. R. Gharpurey and R. G. Meyer, "Modeling and analysis of substrate coupling in integrated circuits," IEEE J. Solid-State Circuits, vol. 31, no. 3, pp. 344-353, Mar. 1996.
102. M. Rahim, B.-Y. Hwang, and J. Foerstner, "Comparison of SOI versus bulk silicon substrate crosstalk properties for mixed-mode IC's," in Proc. IEEE Int. SOI Conf., 1992, pp. 170-171.
103. Y. Hiraoka, S. Matsumoto, and T. Sakai, "New substrate-crosstalk reduction structure using SOI substrate," in Proc. IEEE Int. SOI Conf., 2001, pp. 107-108.
104. J. P. Colinge, J. P. Eggermont, D. Flandre, P. Francis, and P. G. A. Jespers, "Potential of SOI for analog and mixed analog-digital low-power applications," in Proc. IEEE Int. Solid-State Circuits Conf., 1995, pp. 194-195, 366.
105. P. Basedau and Q. Huang, "A post processing method for reducing substrate coupling in mixed-signal integrated circuits," in Proc. Symp. VLSI Circuits, 1995, pp. 41-42.
106. C. P. Liao, D. Tang, and H. C. Lu, "Creation of local semi-insulating regions on semiconductor substrates," U.S., 6046109, Apr. 4, 2000.
107. C. Liao, M.-N. Liu, and K.-C. Juang, "Cross-talk suppression in mixed-mode ICs by the π technology and the future with an SOC integration platform: Particle-beam stand (PBS)," IEEE Trans. Electron Devices, vol. 50, no. 6, pp. 764-768, Jun. 2003.
108. D. Kosaka, M. Nagata, Y. Hiraoka, I. Imanishi, M. Maeda, Y. Murasaka, and A. Iwata, "Isolation strategy against substrate coupling in CMOS mixed-signal/RF circuits," in Proc. Symp. VLSI Circuits, Jun. 2005, pp. 276-279.
109. P. van Zeijl, J.-W. T. Eikenbroek, P.-P. Vervoort, S. Setty, J. Tangenherg, G. Shipton, E. Kooistra, I. C. Keekstra, D. Belot, K. Visser, E. Bosma, and S. C. Blaakmeer, "A Bluetooth radio in 0.18-μm CMOS," IEEE J. Solid-State Circuits, vol. 37, no. 12, pp. 1679-1687, Dec. 2002.
110. S. S. Mehta, D. Weber, M. Terrovitis, K. Onodera, M. P. Mack, B. J. Kaczynski, H. Samavati, S. H.-M. Jen, W. W. Si, M. Lee, K. Singh, S. Mendis, P. J. Husted, N. Zhang, B. McFarland, D. K. Su, T. H. Meng, and B. A. Wooley, "An 802.11 g WLAN SoC," IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2483-2491, Dec. 2005.
111. S. M. Sinaga, A. Polyakov, M. Bartek, and J. N. Burghartz, "Through-substrate trenches for RF isolation in wafer-level chip-scale package," in Proc. Electronics Packaging Technology Conf., 2004, pp. 13-17.
112. L. Korbes, B. Ficq, and S. Savage, "Resonant forward-biased guard-ring diodes for suppression of substrate noise in mixed-mode CMOS circuits," Electron. Lett., vol. 31, pp. 720-721, Apr. 27, 1995.
113. K. Makie-Fukuda, S. Maeda, T. Tsukada, and T. Matsuura, "Substrate noise reduction using active guard band filters in mixed-signal integrated circuits," in Proc. Symp. VLSI Circuits, 1995, pp. 33-34.
114. _, "Substrate noise reduction using active guard band filters in mixed-signal integrated circuits," IEICE Trans. Fundamentals of Electronics, Communications and Computer Sciences, vol. E80-A, pp. 313-320, Feb. 1997.
115. H. H. Y. Chan and Z. Zilic, "Substrate coupled noise reduction and active noise suppression circuits for mixed-signal system-on-a-chip designs," in Proc. IEEE Midwest Symp. Circuits Syst. 2001, pp. 154-157.
116. K. Makie-Fukuda, T. Kikuchi, T. Matsuura, and M. Hotta, "Measurement of digital noise in mixed-signal integrated circuits," IEEE J. Solid-State Circuits, vol. 30, no. 2, pp. 87-92, Feb. 1995.
117. K. Makie-Fukuda, T. Anbo, T. Tsukada, T. Matsuura, and M. Hotta, "Voltage-comparator-based measurement of equivalently sampled substrate noise waveforms in mixed-signal integrated circuits," in Proc. Symp. VLSI Circuits, 1995, pp. 39-40.
118. _, "Voltage-comparator-based measurement of equivalently sampled substrate noise waveform in mixed-signal integrated circuits," IEEE J. Solid-State Circuits, vol. 31, no. 5, pp. 726-731, May 1996.
119. M. van Heijningen, J. Complet, P. Wambacq, S. Donnay, M. G. E. Engels, and I. Bolsens, "Analysis and experimental verification of digital substrate noise generation for epi-type substrates," IEEE J. Solid-State Circuits, vol. 35, pp. 1002-1008, Jul. 2000.
120. Y. Rolain, W. Van Moer, G. Vandersteen, and M. Van Heijningen, "Measuring mixed signal substrate coupling," in Proc. IEEE Instrum. Measure. Technol. Conf., 2000, pp. 855-859.
121. W. K. Chu, N. Verghese, H.-J. Cho, K. Shimazaki, H. Tsujikawa, S. Hirano, S. Doushoh, M. Nagata, A. Iwata, and T. Ohmoto, "A substrate noise analysis methodology for large-scale mixed-signal ICs," in Proc. JEEE Custom Integrated Circuits Conf., 2003, pp. 369-372.
122. M. Nagata, M. Fukazawa, N. Hamanishi, M. Shiochi, T. Iida, J. Watanabe, Y. Murasaka, and A. Iwata, "Substrate integrity beyond I GHz," in Proc. IEEE Int. Solid-State Circuits Conf., 2005, pp. 266-267, 597.
123. G. A. Rezvani and J. Tao, "Substrate isolation in 0.18 μm CMOS technology," in Proc. Int. Conf. Microelectronic Test Structures, 2005, pp. 131-136.
124. L. S. Ishak, R. A. Keating, and C. K. Chakrabarty, "RF substrate noise characterization for CMOS 0.18 μm," in Proc. RF Microwave Conf., 2004, pp. 60-63.
125. K. Makie-Fukuda and T. Tsukada, "On-chip active guard band filters to suppress substrate-coupling noise in analog and digital mixed-signal integrated circuits," in Proc. Symp. VLSI Circuits, 1999, pp. 57-60.
126. T. Liu, J. D. Carothers, and W. T. Holman, "Active substrate coupling noise reduction method for ICs," Electron. Lett., vol. 35, pp. 1633-1634, Sep. 19, 1999.
127. R. T. L. Saez, M. Kayal, and M. Declercq, "CMOS current steering logic: Toward a matured technique for mixed-mode applications," in Proc. IEEE Custom Integrated Circuits Conf., 1997, pp. 349-352.
128. M. Nagata, K. Hijikata, J. Nagai, T. Morie, and A. Iwata, "Reduced substrate noise digital design for improving embedded analog performance," in Proc. IEEE Int. Solid-Slate Circuits Conf., 2000, pp. 224-225, 459.
129. M. Nagata, J. Nagai, K. Hijikata, T. Morie, and A. Iwata, "Physical design guides for substrate noise reduction in CMOS digital circuits," IEEE J. Solid-State Circuits, vol. 36, no. 3, pp. 539-549, Mar. 2001.
130. M. Badaroglu, M. van Heijningen, V. Gravot, J. Complet, S. Donnay, G. G. E. Gielen, and H. J. De Man, "Methodolgy and experimental verification for substrate noise reduction in CMOS mixed-signal ICs with synchronous digital circuits," IEEE J. Solid-State Circuits, vol. 37, no. 11, pp. 1383-1395, Nov. 2002.