Modeling techniques and verification methodologies for substrate coupling effects in mixed-signal system-on-chip designs

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 23, Issue 6, 2004, Pages 823-836

  Koukab, Adil ^a   Banerjee, Kaustav ^b   Declercq, Michel ^a  

^a EPFL   (Switzerland)

^b University of California   (United States)

Author keywords

Mixed signal ICs; RF designs; Substrate noise; System on chip; Transceiver design; Verification

Indexed keywords

ALGORITHMS; COMPUTER AIDED DESIGN; COMPUTER SIMULATION; FINITE DIFFERENCE METHOD; FOURIER TRANSFORMS; ITERATIVE METHODS; MICROPROCESSOR CHIPS; OPTIMIZATION; OSCILLATORS (ELECTRONIC); SIGNAL THEORY; SPURIOUS SIGNAL NOISE; TOPOLOGY; TRANSCEIVERS; VOLTAGE CONTROL;

MIXED-SIGNAL IC; RF DESIGNS; SUBSTRATE NOISE; SYSTEM-ON-CHIP; VERIFICATION;

INTEGRATED CIRCUITS;

EID: 2942657685     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2004.828117     Document Type: Article

References (27)

1. K. Kundert, H. Chang, D. Jefferies, G. Lamant, E. Malavasi, and F. Sendig, "Design of mixed-signal system-om-a-chip," IEEE Trans. Computer-Aided Design, vol. 19, pp. 1561-1571, Dec. 2000.
2. N. K. Verghese, T. J. Schmerbeck, and D. J. Allstot, Simulation Techniques and Solutions for Mixed-Signal Coupling in Integrated Circuits. Norwell, MA: Kluwer, 1995.
3. A. Hajimiri and T. H. Lee, The Design of Low Noise Oscillators. Norwell, MA: Kluwer, 1999.
4. F. Herzel and B. Razavi, "A study of oscillator jitter due to supply and substrate noise," IEEE Trans. Circuits Syst. II, vol. 46, pp. 56-62, Jan. 1999.
5. A. Koukab, M. Declercq, and C. Dehollain, "Analysis and improvement of the noise immunity in a single-chip super-regenerative tranceiver," IEE Proc. Circuits Devices Syst., vol. 148, pp. 250-254, 2001.
6. N. K. Verghese and D. J. Allstot, "Computer-aided design considerations for mixed-signal coupling in RF integrated circuits," IEEE J. Solid-State Circuits, vol. 33, pp. 314-323, Mar. 1998.
7. M. Nagata, J. Nagai, K. Hijikata, T. Morie, and A. Iwata, "Physical design guides for substrate noise reduction in CMOS digital circuits," IEEE J. Solid-State Circuits, vol. 36, pp. 539-549, Mar. 2001.
8. A. Koukab, C. Dehollain, and M. Declercq, "HSpeedEx: A high-speed extractor for substrate noise analysis in complex mixed-signal SOC," in Proc. Design Automation Conf., 2002, pp. 767-770.
9. R. Gharpurey and R. G. Meyer, "Modeling and analysis of substrate coupling in integrated circuits," IEEE J. Solid-State Circuits, vol. 31, pp. 344-353, Mar. 1996.
10. A. M. Niknejad, R. Gharpurey, and R. G. Meyer, "Numerically stable Green function for modeling and analysis of substrate coupling in integrated circuits," IEEE Trans. Computer-Aided Design, vol. 17, pp. 305-31, Apr. 1998.
11. J. R. Phillips and L. M. Silveira, "Simulation approaches for strongly coupled interconnect systems," in Proc. IEEE/ACM Int. Conf. Computer-Aided Design, 2001, pp. 430-437.
12. J. Kanapka, J. Phillips, and J. White, "Fast methods for extraction and sparsification of substrate coupling," in Proc. Design Automation Conf., 2000, pp. 738-743.
13. F. Clément, "Computer aided analysis of parasitic substrate coupling in mixed digital-analog cmos integrated circuits," Ph.D. dissertation, Swiss Fed. Inst. of Technol., Lausanne, Switzerland, 1996.
14. K. Nabros and J. White, "Fast capacitance extraction of general three-dimensional structures," IEEE Trans. Microwave Theory Tech., vol. 40, pp. 1496-1507, June 1992.
15. 3: A fast integral equation solver for efficient 3-dimensional extraction," in IEEE/ACM Int. Conf. Computer-Aided Design, 1997, pp. 448-455.
16. J. R. Phillips and L. M. Silveira, "Simulation approaches for strongly coupled interconnect systems," in Proc. IEEE/ACM Int. Conf. Computer-Aided Design, 2001, pp. 430-437.
17. J. Kanapka, J. Phillips, and J. White, "Fast methods for extraction and sparsification of substrate coupling," in Proc. IEEE/ACM Design Automation Conf., 2000, pp. 738-743.
18. A. Koukab, K. Banerjee, and M. Declercq, "Analysis and optimization of substrate noise in single-chip RF transceiver design," in IEEE/ACM Int. Conf. Computer-Aided Design, 2002, pp. 309-316.
19. A. Demir and J. Roychowdhury, "Modeling and simulation of noise in analog/mixed-signal communication systems," in Proc. IEEE Custom Integrated Circuits Conf., 1999, pp. 385-393.
20. E. Charbon, P. Miliozzi, L. P. Carloni, A. Ferrari, and A. Sangiovanni-Vincentilli, "Modeling digital substrate noise injection in mixed-signal IC' s," IEEE Trans. Computer-Aided Design, vol. 18, pp. 301-310, Mar. 1999.
21. M. V. Heijningen, M. Badaroglu, S. Donnay, M. Engels, and I. Bolsens, "High-Level simulation of substrate noise generation including power supply noise coupling," in Proc. Design Automation Conf., 2000, pp. 446-451.
22. P. Favre, N. Joehl, A. Vouilloz, P. Deval, C. Dehollain, and M. Declercq, "A 2 V, 600 μA, 1 GHz, BiCMOS super-regenerative receiver for ISM applications," IEEE J. Solid-State Circuits, vol. 33, pp. 2186-2196, Dec. 1998.
23. N. Joehl, C. Dehollain, P. Favre, P. Deval, and M. Declercq, "A low power 1 GHz super-regenerative tranceiver with time-shred PLL control," IEEE J. Solid-State Circuits, vol. 36, pp. 1025-1031, July 2001.
24. A. Koukab, P. Deval, C. Dehollain, and M. Declercq, "Low noise power supply technique for RF amplifiers," IEEE Trans. Circuits Syst. II, vol. 48, pp. 291-293, Mar. 2001.
25. A. Rofougaran, G. Chang, J. Rael, Y. C. Chang, M. Rofourgaran, J. Chang, M. Djafari, M. K. Ku, E. W. Roth, A. A. Abidi, and H. Samueli, "A single-chip 900-MHz spread-spectrum wireless transceiver in 1-μm CMOS-Part I: Architecture and transmitter design," IEEE J. Solid-State Circuits, vol. 33, pp. 515-534, Apr. 1998.
26. B. A. Floyd, C. M. Hung, and K. K. O, "The effects of substrate resistivity on RF component and circuit performance," in Proc. IEEE Int. Interconnect Technol. Conf., 2000, pp. 164-166.
27. J. T. Colvin, S. S. Bhatia, and K. K. O, "Effects of substrate resistances on LNA performance and a bondpad structure for reducing the effects in a silicon bipolar technology," IEEE J. Solid-State Circuits, vol. 34, pp. 1339-1344, Sept. 1999.