Substrate integrity beyond 1 GHz

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 48, Issue , 2005, Pages

  Nagata, Makoto ^a   Fukazawa, Mitsuya ^a   Hamanishi, Naoyuki ^b   Shiochi, Masazumi ^b   Iida, Tetsuya ^b   Watanabe, Junichiro ^b   Murasaka, Yoshitaka ^a   Iwata, Atsushi ^a  

^a KOBE UNIVERSITY   (Japan)

^b A R Tec ^*

Author keywords

[No Author keywords available]

Indexed keywords

EID: 28144449500     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. L. M. Franca-Neto et al., "Enabling High-Performance Mixed-Signal System-on-a-Chip in High Performance Logic CMOS Technology," Symp. VLSI Circuits, pp. 164-167, June, 2002.
2. M. v. Heijinigen et al., "Substrate Noise Generation in Complex Digital Systems: Efficient Modeling and Simulation Methodology and Experimental Verification," IEEE J. Solid-State Circuits, vol. 37, no. 8, pp. 1065-1072, Aug., 2002.
3. M. Nagata et al., "Physical Design Guides for Substrate Noise Reduction in CMOS Digital Circuits," IEEE J. Solid-State Circuits, vol. 36, no. 3, pp. 539-549, Mar., 2001.