Isolation strategy against substrate coupling in CMOS mixed-signal/RF circuits

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn 2005, Issue , 2005, Pages 276-279

  Kosaka, Daisuke ^a   Nagata, Makoto ^a   Hiraoka, Yukio ^b   Imanishi, Ikuo ^b   Maeda, Masakatsu ^b   Murasaka, Yoshitaka ^c   Iwata, Atsushi ^c  

^a KOBE UNIVERSITY   (Japan)

^b PANASONIC CORPORATION   (Japan)

^c A R Tec Corporation   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

LAYOUT-LEVEL ISOLATION EFFECTS; MIXED-SIGNAL TECHNOLOGY; RF CIRCUITS; TEST STRUCTURES;

COMPUTER SIMULATION; ELECTRIC CONDUCTIVITY; INTEGRATED CIRCUIT LAYOUT; NATURAL FREQUENCIES; SIGNAL THEORY;

CMOS INTEGRATED CIRCUITS;

EID: 33745164646     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2005.1469385     Document Type: Conference Paper

References (7)

1. N. Verghese and D. Allstot, "Computer-Aided Design Considerations for Mixed-Signal Coupling in RF Integrated Circuits," IEEE J. Solid-State Circuits, Mar. 1998, pp. 314-323.
2. T. Ohguro et al., "Improvement of high resistivity substrate for future mixed analog-digital applications," in Symp. VLSI Technology, June 2002, pp.158-159.
3. K. Benaissa et al., "RF CMOS on High-Resistivity Substrates for System-on-Chip Applications," IEEE Trans. Electron Devices, Mar. 2003, pp. 567-576.
4. T. Blalack et al., "On-chip RF Isolation Techniques," in Bipolar/BiCMOS Circuits and Tech. Mtg., Oct. 2002, pp. 205-211.
5. M. Pfost et al., "An Experimental Study on Substrate Coupling in Bipolar/BiCMOS Technologies," IEEE J. Solid-State Circuits, Oct. 2004, pp. 1755-1763.
6. M. Nagata et al., "Physical Design Guides for Substrate Noise Reduction in CMOS Digital Circuits," IEEE J. Solid-State Circuits, Mar. 2001, pp. 539-549.
7. Y. Murasaka et al., "Substrate Noise Analysis using Fundamental Matrix Computation," in IEEE Int. Symp. Quality Electronic Design, Mar. 2001, pp. 482-487.