메뉴 건너뛰기




Volumn 2000-January, Issue , 2000, Pages 129-134

Lemings: LSI's EMI-noise analysis with gate level simulator

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATION THEORY; DESIGN; ELECTROMAGNETIC PULSE; INTEGRATED CIRCUITS; SIMULATORS;

EID: 0005490915     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2000.838865     Document Type: Conference Paper
Times cited : (18)

References (10)
  • 2
    • 0032659494 scopus 로고    scopus 로고
    • EMI-noise analysis under ASIC design environment
    • Sachio Hayashi et al., "EMI-Noise Analysis under ASIC Design Environment", Proc. ISPD'99, 1999, pp. 16-21.
    • (1999) Proc. ISPD'99 , pp. 16-21
    • Hayashi, S.1
  • 3
    • 0003915801 scopus 로고
    • Memo, ERL-M520, Dept. Electrical Engineering and Computer Sciense, University of California at Berkeley, May 9
    • L. W. Nagal, "SPICE2: a computer program to simulate semiconductor circuits", Memo, ERL-M520, Dept. Electrical Engineering and Computer Sciense, University of California at Berkeley, May 9, 1975
    • (1975) SPICE2: A Computer Program to Simulate Semiconductor Circuits
    • Nagal, L.W.1
  • 6
    • 84950121226 scopus 로고    scopus 로고
    • Noise reduction in 16bit microcomputer
    • Teiji Tokumaru, Nobutaka Kitagawa, "Noise Reduction in 16bit Microcomputer", EMC 1998.6.5 , pp. 75-86.
    • EMC 1998.6.5 , pp. 75-86
    • Tokumaru, T.1    Kitagawa, N.2
  • 7
    • 84950109697 scopus 로고    scopus 로고
    • Radio noise reduction in microcomputer
    • Kouji Ichikawa, "Radio Noise Reduction in Microcomputer", '98 EMC Forum, 1998, pp. 35-44
    • (1998) 98 EMC Forum , pp. 35-44
    • Ichikawa, K.1
  • 8
    • 84950112205 scopus 로고    scopus 로고
    • Verilog hardware description language reference manual (LRM)
    • "Verilog Hardware Description Language Reference Manual (LRM) ", IEEE
    • IEEE
  • 9
    • 0032136312 scopus 로고    scopus 로고
    • Interconnect and circuit modeling techniques for full-chip power noise analysis
    • Aug.
    • Howard H. Chen et al, "Interconnect and Circuit Modeling Techniques for Full-Chip Power Noise Analysis", IEEE transaction on components, packaging and manufacturing technology-PART B, VOL.21, NO.3, Aug. 1998, pp. 209-215.
    • (1998) IEEE Transaction on Components, Packaging and Manufacturing Technology-PART B , vol.21 , Issue.3 , pp. 209-215
    • Chen, H.H.1
  • 10
    • 0030704451 scopus 로고    scopus 로고
    • Power supply noise analysis methodology for deep-submicron VLSI chip design
    • Jun.
    • th DAC, Jun. 1997, pp. 638-644.
    • (1997) th DAC , pp. 638-644
    • Chen, H.H.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.