Reduced substrate noise digital design for improving embedded analog performance

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2000, Pages 224-225

  Nagata, M ^a   Hijikata, K ^a   Nagai, J ^a   Morie, T ^a   Iwata, A ^a  

^a HIROSHIMA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; CAPACITANCE; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; CROSSTALK; ELECTRIC POWER SUPPLIES TO APPARATUS; LOGIC GATES; NOISE ABATEMENT; POLYSILICON;

DISTRIBUTED PARASITIC CAPACITANCES; REDUCED SUPPLY BOUNCE (RSB);

LSI CIRCUITS;

EID: 0034428295     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)

1. Measurements and analyses of substrate noise waveform in mixed signal IC environment
2. Analog logic techniques steer around the noise