Modeling substrate noise generation in CMOS digital integrated circuits

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2002, Pages 501-504

  Nagata, Makoto ^a   Morie, Takashi ^a   Iwata, Atsushi ^a  

^a HIROSHIMA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; CROSSTALK; DIGITAL INTEGRATED CIRCUITS; DIGITAL TO ANALOG CONVERSION; FREQUENCY RESPONSE; GAIN CONTROL; MICROCONTROLLERS; SPURIOUS SIGNAL NOISE; SUBSTRATES; TIME DOMAIN ANALYSIS; WAVEFORM ANALYSIS;

SUBSTRATE NOISE GENERATION;

CMOS INTEGRATED CIRCUITS;

EID: 0036045389     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. Experimental results and modeling techniques for substrate noise in mixed-signal integrated circuits
2. Physical design guides for substrate noise reduction in CMOS digital circuits
3. Effects of power-supply parasitic components on substrate noise generation in large-scale digital circuits
4. Modeling digital substrate noise injection in mixed-signal IC's
5. Lemings: LSI's EMI-Noise analysis with gate level simulator
6. Substrate noise generation in complex digital systems: Efficient modeling and simulation methodology and experimental verification
7. Substrate noise analysis using fundamental matrix computation