Verification techniques for substrate coupling and their application to mixed-signal IC design

IEEE Journal of Solid-State Circuits

Volumn 31, Issue 3, 1996, Pages 354-365

  Verghese, Nishath K ^{a,b,c,e,f,g,h}   Allstot, David J ^a,b,d   Wolfe, Mark A ^e,g,i  

^a IEEE

^b CARNEGIE MELLON UNIVERSITY   (United States)

^c CADENCE DESIGN SYSTEMS   (United States)

^d Oregon State University   (United States)

^e TEXAS INSTRUMENTS   (United States)

^f BIRLA INSTITUTE OF TECHNOLOGY AND SCIENCE   (India)

^g CARNEGIE MELLON UNIVERSITY   (United States)

^h MCGILL UNIVERSITY   (Canada)

ⁱ UNIVERSITY OF TEXAS AT DALLAS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BOUNDARY ELEMENT METHOD; ELECTRIC CONVERTERS; ELECTRIC IMPEDANCE; FINITE DIFFERENCE METHOD; GREEN'S FUNCTION; INTEGRATED CIRCUIT TESTING; MATHEMATICAL MODELS; SPURIOUS SIGNAL NOISE; SUBSTRATES;

MIXED SIGNAL INTEGRATED CIRCUITS; SUBSTRATE COUPLED NOISE; SUBSTRATE COUPLING; TRUNCATED SERIES EXPANSIONS; VERIFICATION;

INTEGRATED CIRCUIT LAYOUT;

EID: 0030110603     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.494197     Document Type: Article

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