Power supply noise suppression via clock skew scheduling

Proceedings - International Symposium on Quality Electronic Design, ISQED

Volumn 2002-January, Issue , 2002, Pages 355-360

  Lam, W C D ^a   Koh, Cheng Kok ^a   Tsao, C W A ^b  

^a PURDUE UNIVERSITY   (United States)

^b Celestry Design Technologies Inc   (United States)

Author keywords

Additive white noise; Circuit noise; Clocks; Contracts; Flip flops; Pins; Power supplies; Routing; Switches; Voltage

Indexed keywords

CONTRACTS; ELECTRIC CLOCKS; ELECTRIC POTENTIAL; FLIP FLOP CIRCUITS; GRAPHIC METHODS; SCHEDULING; SWITCHES; WHITE NOISE;

ADDITIVE WHITE NOISE; CIRCUIT NOISE; PINS; POWER SUPPLY; ROUTING;

CLOCKS;

EID: 0037776791     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2002.996772     Document Type: Conference Paper

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