Modeling of substrate noise coupling for nMOS transistors in heavily doped substrates

IEEE Transactions on Electron Devices

Volumn 52, Issue 8, 2005, Pages 1880-1886

  Hsu, Shuching ^a,b   Fiez, Terri S ^a   Mayaram, Kartikeya ^a  

^a 1148 Kelley Engineering Center Corvallis   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

Integrated circuit noise; Modeling of noise coupling; Substrate coupling; Substrate noise; Substrate parasitic extraction

Indexed keywords

COMPUTER SIMULATION; INTEGRATED CIRCUITS; MATHEMATICAL MODELS; SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR DEVICE STRUCTURES; SEMICONDUCTOR DOPING; SPURIOUS SIGNAL NOISE; SUBSTRATES;

INTEGRATED CIRCUIT NOISE; SUBSTRATE NOISE COUPLING; SUBSTRATE PARASITIC EXTRACTION;

MOSFET DEVICES;

EID: 23344448394     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2005.852171     Document Type: Article

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