Substrate isolation in 0.18um CMOS technology

IEEE International Conference on Microelectronic Test Structures

Volumn , Issue , 2005, Pages 131-136

  Rezvani, G Ali ^a   Tao, Jon ^a  

^a RF Micro Devices   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DEEP NWELL (DNW); SUBSTRATE COUPLING; SUBSTRATE ISOLATION;

MICROELECTRONICS; SPURIOUS SIGNAL NOISE;

CMOS INTEGRATED CIRCUITS;

EID: 27644519471     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. L.E. Lason, "Integrated circuit technology options for RFIC's present and future directions", IEEE Journal of Solid State Circuits, Col. 33, no. 3, 387-399, 1988
2. J.P. Raskin, A. Viivani, D. Flandre, and J. P. Colinge, "Substrate Cross Talk Reduction using SOI Technology", IEEE Transaction on Electron Devices, Vol. 44, no.12, 2252-2261, 1997
3. W. K. Yeh, S. M. Chen, and Y.K. Fang, "Substrate Noise Coupling Characterization and Efficient Suppression in CMOS Technology", IEEE Transactions on Electron Devices, Vol. 51, no. 5, 817-819, 2004