Physical design guides for substrate noise reduction in CMOS digital circuits

IEEE Journal of Solid-State Circuits

Volumn 36, Issue 3, 2001, Pages 539-549

  Nagata, M ^a   Nagai, J ^a   Hijikata, K ^a   Morie, T ^a   Iwata, A ^a  

^a HIROSHIMA UNIVERSITY   (Japan)

Author keywords

Mixed analog digital integrated circuits; Power supply current modeling; Reduced supply bounce CMOS circuit; Signal integrity; Substrate coupling; Substrate measurements; Substrate noise reduction

Indexed keywords

CAPACITANCE; DIGITAL INTEGRATED CIRCUITS; ELECTRIC CURRENTS; INTEGRATED CIRCUIT LAYOUT; LOGIC CIRCUITS; NOISE ABATEMENT; POWER SUPPLY CIRCUITS; TIME SERIES ANALYSIS;

ANALOG INTEGRATED CIRCUITS;

CMOS INTEGRATED CIRCUITS;

EID: 0035274508     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.910494     Document Type: Article

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