SWAN: High-level simulation methodology for digital substrate noise generation

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 14, Issue 1, 2006, Pages 23-32

  Badaroglu, Mustafa ^a,b   Van Der Plas, Geert ^a,b   Wambacq, Piet ^a,b,c,e   Donnay, Stéphane ^a,b,f   Gielen, Georges G E ^a,d,g   De Man, Hugo J ^a,b,d,h  

^a IEEE   (Belgium)

^b IMEC   (Belgium)

^c VRIJE UNIVERSITEIT BRUSSEL   (Belgium)

^d UNIVERSITY OF LEUVEN   (Belgium)

^e FREE UNIVERSITY OF BRUSSELS   (Belgium)

^f Technical Program Committee of the European Solid State Circuits Conference (ESSCIRC)

^g Technical Program Committee of the European Solid State Circuits Conference ^*

^h Royal Academy of Sciences   (Belgium)

Author keywords

Ground bounce; High level simulation; Macromodel; Mixed analog digital ics; Substrate noise

Indexed keywords

GROUND BOUNCE; HIGH-LEVEL SIMULATION; MACROMODEL; MIXED ANALOG-DIGITAL IC; SUBSTRATE NOISE;

DIGITAL CIRCUITS; RESONANCE; SWITCHING SYSTEMS; TRANSISTORS; WAVEFORM ANALYSIS;

NOISE GENERATORS;

EID: 33644981418     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2005.863191     Document Type: Article

References (17)

1. P. T. M. van Zeijl et al., "A Bluetooth radio in 0.18 μm CMOS," IEEE J. Solid-State Circuits, vol. 37, no. 12, pp. 1679-1687, Dec. 2002.
2. S. Donnay and G. Gielen, Eds., Substrate Noise Coupling in Mixed-Signal ASICs. Norwell, MA: Kluwer, 2003.
3. S. Mitra, R. A. Rutenbar, L. R. Carley, and D. J. Allstot, "A methodology for rapid estimation of substrate-coupled switching noise," in Proc. IEEE Custom Integrated Circuits Conf., May 1995, pp. 129-132.
4. M. Badaroglu, P. Wambacq, G. Van der Plas, S. Donnay, G. Gielen, and H. De Man, "Evolution of substrate noise generation mechanisms with CMOS technology scaling," IEEE Trans. Circuits Syst. I, Reg. Papers, to be published.
5. E. Charbon, P. Miliozzi, L. P. Carloni, A. Ferrari, and A. Sangiovanni-Vincentelli, "Modeling digital substrate noise injection in mixed-signal ICs," IEEE Trans. Computer-Aided Design Integr. Circuits Syst., vol. 18, no. 3, pp. 301-310, Mar. 1999.
6. R. Murgai, S. Reddy, T. Miyoshi, T. Horie, and M. Tahoori, "Sensitivity-based modeling and methodology for full-chip substrate noise analysis," in Proc. Design, Automation Test Europe Conf. Exhibit., vol. 1, Feb. 2004, pp. 610-615.
7. M. Badaroglu, P. Wambacq, G. Van der Plas, S. Donnay, G. Gielen, and H. De Man, "Digital ground bounce reduction by supply current shaping and clock frequency modulation," IEEE Trans. Computer-Aided Design Integr. Circuits Syst., vol. 24, no. 1, pp. 65-76, Jan. 2005.
8. M. van Heijningen, M. Badaroglu, S. Donnay, G. Gielen, and H. De Man, "Substrate noise generation in complex digital systems: Efficient modeling and simulation methodology and experimental verification," IEEE J. Solid-State Circuits, vol. 37, no. 8, pp. 1065-1072, Aug. 2002.
9. M. Badaroglu, S. Donnay, H. De Man, Y. Zinzius, G. Gielen, T. Fonden, and S. Signell, "Modeling and experimental verification of substrate noise generation in a 220-KGates WLAN system-on-chip with multiple supplies," IEEE J. Solid-State Circuits, vol. 38, no. 7, pp. 1250-1260, Jul. 2003.
10. M. Badaroglu, P. Wambacq, G. Van der Plas, L. Balasubramanian, K. Tin, S. Donnay, G. Gielen, and H. De Man, "Digital circuit capacitance and switching analysis for ground bounce in IC's with a high-ohmic substrate," IEEE J. Solid-State Circuits, vol. 38, no. 7, pp. 1119-1130, Jul. 2004.
11. G. Van der Plas, M. Badaroglu, G. Vandersteen, P. Dobrovolny, P. Wambacq, S. Donnay, G. Gielen, and H. De Man, "High-level simulation of substrate noise in high-ohmic substrates with interconnect and supply effects," in Proc. ACM/IEEE Design Automation Conf., Jun. 2004, pp. 854-859.
12. Substrate Noise Analyst Tool [Online]. Available: www.cadence.com
13. R. Singh, "A review of substrate coupling issues and modeling strategies," in Proc. IEEE Custom Integrated Circuits Conf., May 1999, pp. 491-499.
14. A. Nardi, H. Zeng, J. L. Garrett, L. Daniel, and A. L. Sangiovanni-Vincentelli, "A methodology for the computation of an upper bound on noise current spectrum of CMOS switching activity," in Proc. IEEE/ACM Int. Conf. Computer Aided Design, Nov. 2003, pp. 778-785.
15. M. Badaroglu, M. van Heijningen, V. Gravot, S. Donnay, H. De Man, G. Gielen, M. Engels, and I. Bolsens, "High-level simulation of substrate noise generation from large digital circuits with multiple supplies," in Proc. Design, Automation Test Europe Conf. Exhibit., Mar. 2001, pp. 326-330.
16. G. Van der Plas, C. Soens, M. Badaroglu, P. Wambacq, and S. Donnay, "Modeling and experimental verification of substrate coupling and isolation techniques in mixed-signal ICs on a lightly-doped substrate," in Proc. VLSI Circuits Symp., Jun. 2005, pp. 280-283.
17. J. M. Wang and T. V. Nguyen, "Extended Krylov subspace method for reduced order analysis of linear circuits with multiple sources," in Proc. ACM/IEEE Design Automation Conf., Jun. 2000, pp. 247-252.