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Volumn 2, Issue , 2005, Pages 819-823

Substrate noise modeling in early floorplanning of MS-SOCs

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; ELECTRIC SIGNAL SYSTEMS; MIXED SIGNAL INTEGRATED CIRCUITS; SUBSTRATES; SYSTEM-ON-CHIP;

EID: 33748619104     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1120725.1121025     Document Type: Conference Paper
Times cited : (8)

References (15)
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  • 2
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    • C. Lin, D. M. W. Leenaerts, "A New Efficient Method for Substrate-Aware Device-Level Placement," Proc, Asia and South Pacific DAC, 2000, pp. 533-536.
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  • 3
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    • A methodology for the computation of an upper bound on noise current spectrum of CMOS switching activity
    • A. Nardi, et al., "A Methodology for the Computation of an Upper Bound on Noise Current Spectrum of CMOS Switching Activity," ICCAD'03,pp. 778,2003.
    • (2003) ICCAD'03 , pp. 778
    • Nardi, A.1
  • 4
    • 0036684625 scopus 로고    scopus 로고
    • Substrate noise generation in complex digital systems: Efficient modeling and simulation methodology and experimental verification
    • M. van Heijningen et al., "Substrate Noise Generation in Complex Digital Systems: Efficient Modeling and Simulation Methodology and Experimental Verification," IEEE J. Solid-State Ore, vol. 37, pp. 1065-1072, 2002.
    • (2002) IEEE J. Solid-State Ore , vol.37 , pp. 1065-1072
    • Van Heijningen, M.1
  • 5
    • 0034228948 scopus 로고    scopus 로고
    • Analysis and experimental verification of digital substrate noise generation for epi-type substrates
    • M. van Heijningen et al., "Analysis and Experimental Verification of Digital Substrate Noise Generation for Epi-Type Substrates," IEEE J. Solid-Slate Ore., vol. 35, pp. 1002-1008, 2000.
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    • Van Heijningen, M.1
  • 6
    • 0036857246 scopus 로고    scopus 로고
    • Methodology and experimental verification for substrate noise reduction in CMOS mixed-signal ics with synchronous digital circuits
    • M. Badaroglu et al., "Methodology and Experimental Verification for Substrate Noise Reduction in CMOS Mixed-Signal ICs With Synchronous Digital Circuits," IEEE Journal of Solid-State Circuits, vol. 37, pp. 1383-1394, 2001.
    • (2001) IEEE Journal of Solid-State Circuits , vol.37 , pp. 1383-1394
    • Badaroglu, M.1
  • 9
    • 84942511731 scopus 로고    scopus 로고
    • RF performance degradation due to coupling of digital swithing-noise in lightly doped substrates
    • C. Soens et al., "RF Performance Degradation Due to Coupling of Digital Swithing-Noise in Lightly Doped Substrates," Proc. Southwest Symposium on Mixed-Signal Design, 2003, pp. 127-132.
    • (2003) Proc. Southwest Symposium on Mixed-Signal Design , pp. 127-132
    • Soens, C.1
  • 11
    • 0033092662 scopus 로고    scopus 로고
    • Modeling digital substrate noise injection in mixed-signal IC's
    • E. Charbon et al., "Modeling Digital Substrate Noise Injection in Mixed-Signal IC's," IEEE Trans on CAD, vol. 18, pp.301-310,1999.
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  • 12
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  • 13
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    • A scalable substrate noise coupling model for design of mixed-signal ICs
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  • 14
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  • 15
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    • Wang, B.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.