Characterizing the effects of the PLL jitter due to substrate noise in discrete-time delta-sigma modulators

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 52, Issue 6, 2005, Pages 1073-1085

  Heydari, Payam ^a  

^a University of California at Irvine   (United States)

Author keywords

Jitter; Oversampling datat converter; Phase noise; Phase locked loop (PLL); Substrate noise; modulator

Indexed keywords

CAPACITORS; CMOS INTEGRATED CIRCUITS; ELECTRIC INVERTERS; JITTER; MATHEMATICAL MODELS; PHASE LOCKED LOOPS; RANDOM PROCESSES; SIGNAL TO NOISE RATIO; SPURIOUS SIGNAL NOISE;

OVERSAMPLING DATA CONVERTER; PHASE NOISE; SUBSTRATE NOISE;

DELTA SIGMA MODULATION;

EID: 22144448631     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2005.849118     Document Type: Article

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