Estimating phase-locked loop jitter due to substrate coupling: A cyclostationary approach

Proceedings - 5th International Symposium on Quality Electronic Design, ISQUED 2004

Volumn , Issue , 2004, Pages 309-314

  Chan, Henry H Y ^a   Zilic, Zeljko ^a  

^a MCGILL UNIVERSITY   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; JITTER; MICROPROCESSOR CHIPS; OSCILLATORS (ELECTRONIC); SPURIOUS SIGNAL NOISE;

JITTER SIMULATIONS; NOISE TO JITTER TRANSFER; RING OSCILLATORS; SYSTEM ON CHIPS (SOC);

PHASE LOCKED LOOPS;

EID: 2942644545     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2004.1283691     Document Type: Conference Paper

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