Effects of power-supply parasitic components on substrate noise generation in large-scale digital circuits

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue CIRCUITS SYMP., 2001, Pages 159-162

  Nagata, M ^a   Ohmoto, T ^a   Murasaka, Y ^a   Morie, T ^a   Iwata, A ^a  

^a HIROSHIMA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ATTENUATION; CAPACITANCE; CMOS INTEGRATED CIRCUITS; ELECTRIC IMPEDANCE; ELECTRIC POWER SUPPLIES TO APPARATUS; SPURIOUS SIGNAL NOISE;

PARASITIC COMPONENTS;

LSI CIRCUITS;

EID: 0034799658     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. Addressing substrate coupling in mixed mode IC's: Simulation and power distribution synthesis
2. Clock skew verification in the presence of IR-drop in the power distribution network
3. Physical design guides for substrate noise reduction in CMOS digital circuits
4. Measurements and analyses of substrate noise waveform in mixed signal IC environment