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Volumn , Issue , 2003, Pages 369-372
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A substrate noise analysis methodology for large-scale mixed-signal ICs
a a a b b b b c d d
c
KOBE UNIVERSITY
(Japan)
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Author keywords
[No Author keywords available]
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Indexed keywords
COMPUTER SIMULATION;
INTEGRATED CIRCUIT LAYOUT;
INTEGRATED CIRCUIT TESTING;
NUMERICAL METHODS;
SENSITIVITY ANALYSIS;
SILICON;
SPURIOUS SIGNAL NOISE;
SUBSTRATES;
INDUCTIVE COUPLING;
NODAL SWITCHING;
SUBSTRATE NOISE ANALYSIS;
SUBSTRATE NOISE WAVEFORM;
CMOS INTEGRATED CIRCUITS;
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EID: 0242443713
PISSN: 08865930
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper |
Times cited : (15)
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References (8)
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