Substrate noise analysis identifies potential problems in mixed-signal and RF designs

IEEE Circuits and Devices Magazine

Volumn 17, Issue 6, 2001, Pages 19-28

  Ponnapalli, Saila ^a   Verghese, Nishath ^b   Chu, Wen Kung ^a   Coram, Geoffrey J ^a  

^a Cadence ^*

^b Cadence   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

SYSTEM-ON-A-CHIP (SOC);

ALGORITHMS; AMPLIFIERS (ELECTRONIC); ANALOG TO DIGITAL CONVERSION; CROSSTALK; INTEGRATED CIRCUITS; MATHEMATICAL MODELS; SPURIOUS SIGNAL NOISE;

CHIP SCALE PACKAGES;

EID: 0035517255     PISSN: 87553996     EISSN: None     Source Type: Journal    
DOI: 10.1109/101.968913     Document Type: Article

References (6)

1. Delta-I noise specification for high-performance computing machine
2. Addressing substrate coupling in mixed-mode ICs: Simulation and power distribution synthesis
3. Modeling digital substrate noise injection in mixed-signal ICs
4. High quality analog CMOS and mixed signal LSI design