-
1
-
-
0027576336
-
Experimental results and modeling techniques for substrate noise in mixed-signal integrated circuits
-
DOI 10.1109/4.210024
-
D. K. Su, M. J. Loinaz, S. Masui, and B. A. Wooley, "Experimental Results and Modeling Techniques for Substrate Noise in Mixed-Signal Integrated Circuits," IEEE J. Solid-State Circuits, Vol. 28, No. 4, pp. 420-430, Apr. 1993. (Pubitemid 23686649)
-
(1993)
IEEE Journal of Solid-State Circuits
, vol.28
, Issue.4
, pp. 420-430
-
-
Su, D.K.1
Loinaz, M.J.2
Masui, S.3
Wooley, B.A.4
-
3
-
-
0028517306
-
A Simple Approach to Modeling Cross-Talk in Integrated Circuits
-
Oct.
-
K. Joardar, "A Simple Approach to Modeling Cross-Talk in Integrated Circuits," IEEE J. Solid-State Circuits, Vol. 29, No. 10, pp.1212-1219, Oct. 1994.
-
(1994)
IEEE J. Solid-State Circuits
, vol.29
, Issue.10
, pp. 1212-1219
-
-
Joardar, K.1
-
4
-
-
0029270756
-
Substrate-Aware Mixed-Signal Macrocell Placement in WRIGHT
-
Mar.
-
S. Mitra, R. A. Rutenbar, L. R. Carley, and D. J. Allstot, "Substrate-Aware Mixed-Signal Macrocell Placement in WRIGHT," IEEE J. Solid-State Circuits, Vol. 30, No. 3, pp. 269-278, Mar. 1995.
-
(1995)
IEEE J. Solid-State Circuits
, vol.30
, Issue.3
, pp. 269-278
-
-
Mitra, S.1
Rutenbar, R.A.2
Carley, L.R.3
Allstot, D.J.4
-
5
-
-
0032026503
-
Computer-Aided Design Considerations for Mixed-Signal Coupling in RF Integrated Circuits
-
Mar.
-
N. K. Verghese and D. J. Allstot, "Computer-Aided Design Considerations for Mixed-Signal Coupling in RF Integrated Circuits," IEEE J. Solid-State Circuits, Vol. 33, No. 3, pp. 314-323, Mar. 1998.
-
(1998)
IEEE J. Solid-State Circuits
, vol.33
, Issue.3
, pp. 314-323
-
-
Verghese, N.K.1
Allstot, D.J.2
-
7
-
-
0033092662
-
Modeling digital substrate noise injection in mixed-signal IC's
-
E. Charbon, P. Miliozzi, L. P. Carloni, A. Ferrari, and A. Sangiovanni-Vincentelli, "Modeling Digital Substrate Noise Injection in Mixed-Signal IC's," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 18, No. 3, pp. 301-310, Mar. 1999. (Pubitemid 129309590)
-
(1999)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
, vol.18
, Issue.3
, pp. 301-310
-
-
Charbon, E.1
Miliozzi, P.2
Carloni, L.P.3
Ferrari, A.4
Sangiovanni-Vincentelli, A.5
-
8
-
-
0028384192
-
Addressing Substrate Coupling in Mixed-Mode IC's: Simulation and Power Distribution Synthesis
-
Mar.
-
B. R. Stanisic, N. K. Verghese, R. A. Rutenbar, L. R. Carley, and D. J. Allstot, "Addressing Substrate Coupling in Mixed-Mode IC's: Simulation and Power Distribution Synthesis," IEEE J. Solid-State Circuits, Vol. 29, No. 3, pp. 226-238, Mar. 1994.
-
(1994)
IEEE J. Solid-State Circuits
, vol.29
, Issue.3
, pp. 226-238
-
-
Stanisic, B.R.1
Verghese, N.K.2
Rutenbar, R.A.3
Carley, L.R.4
Allstot, D.J.5
-
9
-
-
0025414182
-
Asymptotic Waveform Evaluation for Timing Analysis
-
Apr.
-
L. T. Pillage and R. A. Rohler, "Asymptotic Waveform Evaluation for Timing Analysis," IEEE Trans. on Computer-Aided Design, Vol. 9, No. 4, pp. 352-366, Apr. 1993.
-
(1993)
IEEE Trans. on Computer-Aided Design
, vol.9
, Issue.4
, pp. 352-366
-
-
Pillage, L.T.1
Rohler, R.A.2
-
11
-
-
0029227539
-
A Methodology for Rapid Estimation of Substrate-Coupled Switching Noise
-
S. Mitra, R. A. Rutenbar, L. R. Carley, and D. J. Allstot, "A Methodology for Rapid Estimation of Substrate-Coupled Switching Noise," in Proc. IEEE Custom Integrated Circuits Conf., May 1995, pp. 129-132.
-
Proc. IEEE Custom Integrated Circuits Conf., May 1995
, pp. 129-132
-
-
Mitra, S.1
Rutenbar, R.A.2
Carley, L.R.3
Allstot, D.J.4
-
14
-
-
0032633162
-
Substrate Noise Simulation Techniques for Analog-Digital Mixed LSI Design
-
Feb.
-
M. Nagata and A. Iwata, "Substrate Noise Simulation Techniques for Analog-Digital Mixed LSI Design," IEICE Trans. Fundamentals, Vol. E82-A, No. 2, pp. 271-278, Feb. 1999.
-
(1999)
IEICE Trans. Fundamentals
, vol.E82-A
, Issue.2
, pp. 271-278
-
-
Nagata, M.1
Iwata, A.2
-
15
-
-
0032597725
-
Measurements and Analyses of Substrate Noise Waveform in Mixed Signal IC Environment
-
M. Nagata, Y. Kashima, D. Tamura, T. Morie, and A. Iwata, "Measurements and Analyses of Substrate Noise Waveform in Mixed Signal IC Environment," in Proc. IEEE Custom Integrated Circuits Conf., May 1999, pp. 575-578.
-
Proc. IEEE Custom Integrated Circuits Conf., May 1999
, pp. 575-578
-
-
Nagata, M.1
Kashima, Y.2
Tamura, D.3
Morie, T.4
Iwata, A.5
-
16
-
-
0029244952
-
Measurement of Digital Noise in Mixed-Signal Integrated Circuits
-
Feb.
-
K. M. Fukuda, T. Kikuchi, T. Matsuura, and M. Hotta, "Measurement of Digital Noise in Mixed-Signal Integrated Circuits," IEEE J. Solid-State Circuits, Vol. 30, No. 2, pp. 87-92, Feb. 1995.
-
(1995)
IEEE J. Solid-State Circuits
, vol.30
, Issue.2
, pp. 87-92
-
-
Fukuda, K.M.1
Kikuchi, T.2
Matsuura, T.3
Hotta, M.4
-
17
-
-
0030146984
-
Voltage-Comparator-Based Measurement of Equivalently Sampled Substrate Noise Waveforms in Mixed-Signal Integrated Circuits
-
May.
-
K. M. Fukuda, T. Anbo, T. Tsukada, T. Matsuura, and M. Hotta, "Voltage-Comparator-Based Measurement of Equivalently Sampled Substrate Noise Waveforms in Mixed-Signal Integrated Circuits," IEEE J. Solid-State Circuits, Vol. 31, No. 5, pp. 726-731, May. 1996.
-
(1996)
IEEE J. Solid-State Circuits
, vol.31
, Issue.5
, pp. 726-731
-
-
Fukuda, K.M.1
Anbo, T.2
Tsukada, T.3
Matsuura, T.4
Hotta, M.5
-
18
-
-
0031104003
-
Forming Damped LRC Parasitic Circuits in Simultaneously Switched CMOS Output Buffers
-
Mar.
-
T. J. Gabara, W. C. Fischer, J. Harrington, and W. W. Troutman, "Forming Damped LRC Parasitic Circuits in Simultaneously Switched CMOS Output Buffers," IEEE J. Solid-State Circuits, Vol. 32, No. 3, pp. 407-418, Mar. 1997.
-
(1997)
IEEE J. Solid-State Circuits
, vol.32
, Issue.3
, pp. 407-418
-
-
Gabara, T.J.1
Fischer, W.C.2
Harrington, J.3
Troutman, W.W.4
-
19
-
-
0031188074
-
Design strategies and decoupling techniques for reducing the effects of electrical interference in mixed-mode IC's
-
PII S0018920097043709
-
M. Ingels and M. S. J. Steyaert, "Design Strategies and Decoupling Techniques for Reducing the Effects of Electrical Interference in Mixed-Mode IC's," IEEE J. Solid-State Circuits, Vol. 32, No. 7, pp. 1136-1141, Jul. 1997. (Pubitemid 127580572)
-
(1997)
IEEE Journal of Solid-State Circuits
, vol.32
, Issue.7
, pp. 1136-1141
-
-
Ingels, M.1
Steyaert, M.S.J.2
-
21
-
-
0021405731
-
CHIP SUBSTRATE RESISTANCE MODELING TECHNIQUE FOR INTEGRATED CIRCUIT DESIGN
-
T. A. Johnson, R. W. Knepper, V. Marcello, and W. Wang, "Chip Substrate Resistance Modeling Technique for Integrated Circuit Design," IEEE Trans. on Computer-Aided Design, Vol. CAD-3, No. 2, pp. 126-134, Apr. 1984. (Pubitemid 14569857)
-
(1984)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
, vol.CAD-3
, Issue.2
, pp. 126-134
-
-
Johnson, T.A.1
Knepper, R.W.2
Marcello, V.3
Wang, W.4
-
23
-
-
0030110603
-
Verification Techniques for Substrate Coupling and Their Application to Mixed-Signal IC Design
-
Mar.
-
N. K. Verghese, D. J. Allstot and M. A. Wolfe, "Verification Techniques for Substrate Coupling and Their Application to Mixed-Signal IC Design," IEEE J. Solid-State Circuits, Vol. 31, No. 3, pp. 354-365, Mar. 1996.
-
(1996)
IEEE J. Solid-State Circuits
, vol.31
, Issue.3
, pp. 354-365
-
-
Verghese, N.K.1
Allstot, D.J.2
Wolfe, M.A.3
-
24
-
-
0033078939
-
Substrate Optimization Based on Semi-Analytical Techniques
-
Feb.
-
E. Charbon, R. Gharpurey, R. G. Meyer, and A. Sangiovanni-Vincentelli, "Substrate Optimization Based on Semi-Analytical Techniques," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 18, No. 2, pp. 172-190, Feb. 1999.
-
(1999)
IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems
, vol.18
, Issue.2
, pp. 172-190
-
-
Charbon, E.1
Gharpurey, R.2
Meyer, R.G.3
Sangiovanni-Vincentelli, A.4
-
25
-
-
0030110592
-
Modeling and Analysis of Substrate Coupling in Integrated Circuits
-
Mar.
-
R. Gharpurey and R. G. Meyer, "Modeling and Analysis of Substrate Coupling in Integrated Circuits," IEEE J. Solid-State Circuits, Vol. 31, No. 3, pp. 344-353, Mar. 1996.
-
(1996)
IEEE J. Solid-State Circuits
, vol.31
, Issue.3
, pp. 344-353
-
-
Gharpurey, R.1
Meyer, R.G.2
-
27
-
-
0029254102
-
The Effects of Switching Noise on an Oversampling A/D Converter
-
Feb.
-
T. Blalack and B. A. Wooley, "The Effects of Switching Noise on an Oversampling A/D Converter," in ISSCC Dig. Tech. Papers, Feb. 1995, pp. 200-201.
-
(1995)
ISSCC Dig. Tech. Papers
, pp. 200-201
-
-
Blalack, T.1
Wooley, B.A.2
|