Measurements and analyses of substrate noise waveform in mixed-signal 1C environment

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 19, Issue 6, 2000, Pages 671-678

  Nagata, Makoto ^a   Nagai, Jin ^a   Morie, Takashi ^a   Iwata, Atsushi ^a  

^a HIROSHIMA UNIVERSITY   (Japan)

Author keywords

Mixed analog digital integrated circuits; Signal integrity; Substrate coupling; Substrate noise measurements

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPARATOR CIRCUITS; COMPUTER SIMULATION; ELECTRIC POWER SUPPLIES TO APPARATUS; EQUIVALENT CIRCUITS; SEMICONDUCTOR DEVICE TESTING; SUBSTRATES; THRESHOLD VOLTAGE;

LATCH COMPARATOR; SIGNAL INTEGRITY; SOFTWARE PACKAGE SPICE; SUBSTRATE COUPLING; SUBSTRATE NOISE MEASUREMENTS;

SPURIOUS SIGNAL NOISE;

EID: 0033707515     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.848088     Document Type: Article

References (13)

1. T. A. Johnson R. W. Knepper V. Marcello and W. Wang Chip substrate resistance modeling technique for integrated circuit design IEEE Trans. Computer-Aided Design vol. CAD-3 pp. 126-134 Apr. 1984.
2. N. K. Verghese T. J. Schmerbeck and D. J. Allstot Simulation Techniques and Solutions for Mixed-Signal Coupling in Integrated Circuits. Norwell MA: Kluwer Academic 1995.
3. I. L. Wemple and A. T. Yang Integrated circuit substrate coupling models based on voronoi tessellation IEEE Trans. Compute r-Aided Design pp. 1459-1469 Dec. 1995.
4. N. K. Verghese D. J. Allstot and M. A. Wolfe Verification techniques for substrate coupling and their application to mixed-signal 1C design IEEEJ. Solid-State Circuits vol. 31 pp. 354-365 Mar. 1996.
5. R. Gharpurey and R. G. Meyer Modeling and analysis of substrate coupling in integrated circuits IEEE J. Solid-State Circuits vol. 31 pp. 344-353 Mar. 1996.
6. B. R. Stanisic N. K. Verghese R. A. Rutenbar L. R. Carley and D. J. Allstot Addressing substrate coupling in mixed-mode IC's: Simulation and power distribution synthesis IEEE J. Solid-State Circuits vol. 29 pp. 226-238 Mar. 1994.
7. L. T. Pillage and R. A. Rohler Asymptotic waveform evaluation for timing analysis IEEE Trans. Compute r-Aided Design vol. 9 pp. 352-366 Apr. 1993.
8. S. Mitra R. A. Rutenbar L. R. Carley and D. J. Allstot A methodology for rapid estimation of substrate-coupled switching noise in Proc. IEEE Custom-Integrated Circuits Conf. May 1995 pp. 129-132.
9. M. K. Mayes and S. W. Chin All verilog mixed-signal simulator with analog behavioral and noise models in Dig. Tech. Papers Symp. on VLSI Circuits pp. 186-187 June 1996.
10. M. Nagata and A. Iwata A macroscopic substrate noise model for full chip mixed-signal design verification in Dig. Tech. Papers Symp. on VLSI Circuits pp. 37-38 June 1997.
11. Substrate noise simulation techniques for analog-digital mixed LSI design IEICE Trans. Fundamentals vol. E82-A no. 2 pp. 271-278 Feb. 1999.
12. D. K. Su M. J. Loinaz S. Masui and B. A. Wooley Experimental results and modeling techniques for substrate noise in mixed-signal integrated circuits IEEEJ. Solid-State Circuits vol. 28 pp. 420-4130 Apr. 1993.
13. K. M. Fukuda T. Anbo T. Tsukada T. Matsuura and M. Hotta Voltage-comparator-based measurement of equivalently sampled substrate noise waveforms in mixed-signal integrated circuits IEEE J. Solid-State Circuits vol. 31 pp. 726-731 May 1996.