Analysis of the PLL jitter due to power/ground and substrate noise

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 51, Issue 12, 2004, Pages 2404-2416

  Heydari, Payam ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Cyclostationary noise; Jitter; Phase noise; Phase locked loop (PLL); Power ground bounce; Random process; Ring oscillator; Substrate noise; Voltage controlled oscillator (VCO)

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; MATHEMATICAL MODELS; RANDOM PROCESSES; SPURIOUS SIGNAL NOISE; SWITCHING CIRCUITS; TIMING JITTER; VARIABLE FREQUENCY OSCILLATORS; VLSI CIRCUITS;

CYCLOSTATIONARY NOISE; PHASE NOISE; POWER GROUND BOUNCE; RING OSCILLATOR; SUBSTRATE NOISE;

PHASE LOCKED LOOPS;

EID: 10944245707     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2004.838240     Document Type: Article

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