Survey on real-time networks-on-chip

IEEE Transactions on Parallel and Distributed Systems

Volumn 28, Issue 5, 2017, Pages 1500-1517

  Hesham, Salma ^a,b   Rettkowski, Jens ^b   Goehringer, Diana ^b   El Ghany, Mohamed A Abd ^a,c  

^a GERMAN UNIVERSITY IN CAIRO   (Egypt)

^b RUHR UNIVERSITY BOCHUM   (Germany)

^c DARMSTADT UNIVERSITY OF TECHNOLOGY   (Germany)

Author keywords

Multi core single chip multiprocessors; on chip interconnection networks; power management; real time and embedded systems

Indexed keywords

COMPLEX NETWORKS; EMBEDDED SYSTEMS; ENERGY EFFICIENCY; INTEGRATED CIRCUIT DESIGN; INTERACTIVE COMPUTER SYSTEMS; INTERCONNECTION NETWORKS (CIRCUIT SWITCHING); MULTIPROCESSING SYSTEMS; NETWORK-ON-CHIP; POWER MANAGEMENT; QUALITY OF SERVICE; SURVEYS; SYSTEM-ON-CHIP;

ENERGY-EFFICIENT TECHNIQUES; EVALUATION METHODOLOGIES; MULTI PROCESSOR SYSTEMS; MULTI-CORE/SINGLE-CHIP MULTIPROCESSORS; ON-CHIP INTERCONNECTION NETWORK; PERFORMANCE MEASUREMENTS; REAL-TIME AND EMBEDDED SYSTEMS; REAL-TIME APPLICATION;

REAL TIME SYSTEMS;

EID: 85018158686     PISSN: 10459219     EISSN: None     Source Type: Journal    
DOI: 10.1109/TPDS.2016.2623619     Document Type: Review

References (104)

1. Intel many integrated core architecture-advanced. (2011). [Online]. Available: http://www.intel.com, Accessed on: 2015
2. S. Borkar, "Thousand core chips: A technology perspective," in Proc. 44th Annu. Des. Automat. Conf., 2007, pp. 746-749
3. W. J. Dally, and B. Towles, "Route packets not wires: on-chip interconnection networks," in Proc. 38th Annu. Design Autom. Conf., 2001, pp. 684-689
4. W. J. Dally, and B. Towles, Principles, and practices of interconnection networks, Burlington, MA, USA: Morgan Kaufmann, 2003
5. M. A. Abd El Ghany, M. A. El-Moursy, and M. Ismail, "High throughput architecture for high performance NoC," in Proc. Circuits Syst., 2010, pp. 2241-2244
6. T. Bjerregaard, and S. Mahadevan, "A survey of research, and practices of Network-on-chip," ACM Comput. Surveys, vol. 38, no. 1, 2006, Art. no. 1
7. U. Y. Ogras, and R. Marculescu, "Literature survey," in Modeling, Analysis, and Optimization of Network-on-Chip Communication Architectures, vol. 184. Dordrecht, Netherlands: Springer, 2013, pp. 9-32
8. A. Abbas, et al., "A survey on energy-efficient methodologies, and architectures of network-on-chip," Comput. Electr. Eng., vol. 40, no. 8, pp. 333-347, 2014
9. G. Haiyun, "Survey of dynamically reconfigurable network-onchip," in Proc. IEEE Int. Conf. Future Comput. Sci. Appl., 2011, pp. 200-203
10. S. Hesham, J. Rettkowski, D. Goehringer, and M. A. Abd El Ghany, "Survey on real-time network-on-chip architectures," in Proc. 11th Int. Symp. Appl. Reconfigurable Comput., 2015, pp. 191-202
11. P. P. Panda, C. Grecu, M. Jones, A. Ivanov, and R. Saleh, "Performance evaluation, and design trade-offs for network-onchip interconnect architectures," IEEE Trans. Comput., vol. 54, no. 8, pp. 1025-1040, Aug. 2005
12. J. Sparsoe, "Design of networks-on-chip for real-time multi-processor systems-on-chip," in Proc. 12th Int. Conf. Appl. Concurrency Syst. Des., 2012, pp. 1-5
13. J. Zhan, N. Stoimenov, J. Ouyang, L. Thiele, V. Narayanan, and Y. Xie, "Designing energy-efficient NoC for real-time embedded systems through slack optimization," in Proc. 50th ACM/EDAC/IEEE Des. Automat. Conf., 2013, pp. 1-6
14. B. Nikolic, and S. M. Petters, "EDF as an arbitration policy for wormhole-switched priority-preemptive NoCs-myth or fact?," in Proc. 14th Int. Conf. Embedded Softw., 2014, Art. no. 28
15. L. S. Indrusiak, "End-to-end schedulability tests formultiprocessor embedded systems based on networks-on-chip with priority-preemptive arbitration," J. Syst.Archit., vol. 60, no. 7, pp. 553-561, 2014
16. S. Foroutan, Y. Thonnart, and F. Petrot, "An iterative computational technique for performance evaluation of networks-on-chip," IEEE Trans. Comput., vol. 62, no. 8, pp. 1641-1655, Aug. 2013
17. A. E. Kiasari, A. Jatsch, and Z. Lu, "Mathematical formalisms for performance evaluation of networks-on-chip," ACM Comput. Surveys, vol. 45, no. 3, pp. 38: 1-38: 40, 2013
18. K. Goossens, et al., "Guaranteeing the quality of services in networks on chip," in Networks on Chip, A. Jantsch, and H. Tenhunen, Eds. New York, NY, USA: Springer, 2003, pp. 61-82
19. A. Mello, N. Calazans, and F. Moraes, "QoS in Networks-on-Chip-beyond priority, and circuit-switching techniques," in VLSI-SoC: Advanced Topics on Systems on a Chip. Berlin, Germany: Springer, 2007
20. D. Bertozzi, and L. Benini, "Xpipes: A network-on-chip architecture for gigascale systems-on-chip," IEEE Circuits Syst. Mag., vol. 4, no. 2, pp. 18-31, Sep. 2004
21. D. Wiklund, and D. Liu, "SoCBUS: Switched network on chip for hard real time embedded systems," in Proc. Int. Parallel Distrib. Process. Symp., 2003, pp. 78-85
22. P.-H. Pham, J. Park, P. Mau, and C. Kim, "Design, and implementation of backtracking wave-pipeline switch to support guaranteed throughput in network-on-chip," IEEE Trans. VLSI Sys., vol. 20, no. 2, pp. 270-283, Feb. 2012
23. P. T. Wolkotte, G. J. M. Smit, G. K. Rauwerda, and L. T. Smit, "An energy-efficient reconfigurable circuit-switched network-onchip," in Proc. 19th IEEE Int. Parallel Distrib. Process. Symp., 2005, pp. 155a-155a
24. S. Liu, A. Jantsch, and Z. Lu, "Parallel probing: Dynamic, and constant time setup procedure in circuit-switching NoC," in Proc. Des. Automat. Test Europe Conf. Exhib., Mar. 2012, pp. 1289-1294
25. M. D. Harmanci, N. P. Escudero, Y. Leblebici, and P. Ienne, "Quantitative modelling, and comparison of communication schemes to guarantee quality-of-service in networks-on-chip," in Proc. IEEE Int. Symp. Circuits Syst., 2005, pp. 1782-1785
26. Z. Shi, and A. Burns, "Real-time communication analysis for onchip networks with wormhole switching," in Proc. 2nd ACM/IEEE Int. Symp. Netw.-on-Chip , 2008, pp. 161-170
27. Z. Shi, and A. Burns, "Schedulability analysis, and task mapping for real-time on-chip communication," Real-Time Syst., vol. 46, no. 3, pp. 360-385, 2010
28. A. Racu, and L. S. Indrusiak, "Using genetic algorithm to map hard real-time on NoC-based systems," in Proc. 7th Int. Workshop Reconfigurable Commun. Centric Syst.-on-Chip, 2012, pp. 1-8
29. I. S. Bonilha, O. M. D. Santos, and L. Indrusiak, "Heuristics for mapping real-time applications to NoC-based architectures using genetic algorithms," in Proc. Brazilian Symp. Comput. Syst. Eng., 2014, pp. 144-149
30. N. M. S. M. Sayuti, and L. S. Indrusiak, "A function for hard realtime system search-based task mapping optimization," in Proc. IEEE 18th Int. Symp. Real-Time Distrib. Comput., 2015, pp. 66-73
31. E. Bolotin, I. Cidon, R. Ginosar, and A. Kolodny, "QNoC: QoS architecture, and design process for network on chip," J. Syst. Archit., vol. 50, no. 2/3, pp. 105-128, 2004
32. J. Diemer, R. Ernst, and M. Kauschke, "Efficient throughputguarantees for latency-sensitive networks-on-chip," in Proc. 15th Asia South Pacific Des. Automat. Conf., 2010, pp. 529-534
33. K. Cheshmi, J. Trajkovic, M. Soltaniyeh, and S. Mohammadi, "Quota setting router architecture for quality of service in GALS NoC," in Proc. Int. Symp. Rapid Syst. Prototyping., 2013, pp. 44-50
34. S.-H. Lo, et al., "QoS aware BiNoC architecture," in Proc. IEEE Int. Symp. Parallel Distrib. Process., 2010, pp. 1-10
35. E. d. F. Correa, L. A. d. P. e. Silva, F.R. Wagner, and L. Carro, "Fitting the router characteristics in NoCs to meet QoS requirements," in Proc. 20th Annu. Conf. Integr. Circuits Syst.Des., 2007
36. C.-H. Lu, K.-C. Chiang, and P.-A. Hsiun, "Round-based priority arbitration for predictable, and reconfigurable Network-on-Chip," in Proc. 8th IEEE Int. Conf. Field-Programmable Technol., 2009, pp. 403-406
37. B. Sudev, L. S. Indrusiak, and J. Harbin, "Network-on-chip packet prioritisation based on instantaneous slack awareness," in Proc. IEEE 13th Int. Conf. Ind. Informat., 2015, pp. 227-232
38. B. Sudev, and L. Indrusiak, "Low overhead predictability enhancement in non-preemptive network-on-chip routers using Priority Forwarded Packet Splitting," in Proc. IEEE 9th Int. Symp. Reconfigurable Commun.-Centric Syst.-on-Chip, 2014, pp. 1-8
39. Z. Lu, and A. Jantsch, "Slot allocation using logical networks for TDM virtual-circuit configuration for network-on-chip," in Proc. IEEE/ACM Int. Conf. Comput.-Aided Des., 2007, pp. 18-25
40. K. Goossens, J. Dielissen, and A. Radulescu, "The Athereal network on chip: Concepts, architectures, and implementations," IEEE Des. Test Comput., vol. 22, no. 5, pp. 414-421, Sep./Oct. 2005
41. N. Concer, A. Vesco, R. Scopigno, and L. Carloni, "A dynamic, and distributed TDM slot-scheduling protocol for QoS-oriented Networks-on-Chip," in Proc. IEEE 29th Int. Conf. Comput. Des., 2011, pp. 31-38
42. M. Millberg, E. Nilsson, R. Thid, and A. Jantsch, "Guaranteed bandwidth using looped containers in temporally disjoint networks within the nostrum network on chip," in Proc. Des. Autom. Test Europe Conf. Exhib., 2004, pp. 890-895
43. A. Hansson, M. Subbaraman, and K. Goossens, "Aelig;lite: A flit-synchronous network on chip with composable, and predictable services," inProc. Des. Autom. Test EuropeConf.Exhib., 2009, pp. 250-255
44. R. A. Stefan, A. Molnos, and K. Goossens, "dAlite: A TDM NoC supporting QoS, multicast, and fast connection set-up," IEEE Trans. Comput., vol. 63, no. 3, pp. 583-594, Mar. 2014
45. K. Goossens, and A. Hansson, "The aethereal network on chip after ten years: Goals, evolution, lessons, and future," in Proc. 47th ACM/IEEE Des. Autom. Conf., 2010, pp. 306-311
46. E. Kasapaki, M. Schoeberl, R. B. Sørensen, C.Müller, K. Goossens, and J. Sparsø, "Argo: A real-time network-on-chip architecture with an efficient GALS implementation," IEEE Trans. Very Large Scale Integration (VLSI), vol. 24 no. 2, pp. 479-492, Feb. 2016
47. H. M. G. Wassel, et al., "SurfNoC: a low latency, and probably non-interfering approach to secure networks-on-chip," in Proc. ISCA, 2013, pp. 583-594
48. A. Psarras, I. Seitanidis, C. Nicopoulos, and G. Dimitrakopoulos, "PhaseNoC: TDM scheduling at the virtual-channel level for efficient network traffic isolation," in Proc. Des. Autom. Test Europe Conf. Exhib., 2015, pp. 1090-1095
49. T. Bjerregaard, and J. Sparso, "A router architecture for connection-oriented service guarantees in the MANGO clockless network-on-chip," in Proc. Des. Autom. Test Europe Conf. Exhib., 2005, pp. 1226-1231
50. J. Heisswolf, R. Konig, M. Kupper, and J. Becker, "Providing multiple hard latency, and throughput guarantees for packetswitching networks on chip," Comput. Electr. Eng., vol. 39, no. 8, pp. 2603-2622, 2013
51. A. Lusala, and J. Legat, "A hybrid NoC combining SDM-TDMbased circuit-switching with packet-switching for real-time applications," inProc. IEEE10th Int. NewCircuits. Syst.Conf., 2012, pp. 17-20
52. F. Pakdaman, A. Mazloumi, and M. Modarressi, "Integrated circuit-packet-switching NoC with efficient circuit setup mechanism," J. Supercomputing, vol. 71, pp. 1-21, 2014
53. J. Yin, P. Zhou, S. Sapatnekar, and A. Zhai, "Energy-efficient time-division multiplexed hybrid-switched NoC for heterogeneous multicore systems," in Proc. IEEE 28th Int. Parallel Distrib. Process. Symp., 2014, pp. 293-303
54. D. Goehringer, O. Oey, M. Huebner, and J. Becker, "Heterogeneous, and runtime parameterizable star-wheels network-on-chip," in Proc. Int. Conf. Embedded Comput. Syst., 2011, pp. 380-387
55. M. Ruaro, E. A. Carara, and F. G. Moraes, "Runtime adaptive circuit switching, and flow priority in NoC-Based MPSoCs," IEEE Trans. VLSI Syst., vol. 23, no. 6, pp. 1077-1088, Jun. 2015
56. J. P. Diguet, "Self-adaptive network on chips," in Proc. 27th Symp. Integr. Circuits Syst. Des., 2014, Art. no. 24
57. J. Heisswolf, M. Singh, M. Kupper, R. Konig, and J. Becker, "Rerouting: Scalable NoC self-optimization by distributed hardware-based connection reallocation," in Proc. Int. Conf. Reconfigurable Comput. FPGAs, 2013, pp. 1-8
58. J. Zhan, et al., "Optimizing the NoC slack through voltage, and frequency scaling in hard real-time embedded systems," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 33, no. 11, pp. 1632-1643, Nov. 2014
59. M. D. Grammatikakis, A. Papagrigoriou, P. Petrakis, and G. Kornaros, "Non-intrusive NoC DFS for soft real-time multimedia applications," in Proc. 16th Euromicro Conf. Dig. Syst. Des., 2013, pp. 60-63
60. H. He, G. Yang, and J. Hu, "Algorithms for power-efficient QoS in application specific NoCs," in Proc. IEEE/ACM Int. Symp. Low Power Electron. Des., 2014, pp. 165-170
61. M. N. S. M. Sayuti, L. S. Indrusiak, and A. Gracia-Ortiz, "An optimization Algorithm for minimizing energy dissipation in NoCbased hard real-time embedded systems," in Proc. 21st Int. Conf. Real-Time Netw. Syst., 2013, pp. 3-12
62. M. N. S. M. Sayuti, and L. S. Indrusiak, "Real-time low power task mapping in networks-on-chip," in Proc. IEEE Comput. Soc. Annu. Symp. VLSI, Aug. 2013, pp. 14-19
63. J. Palma, L. S. Indrusiak, F. G. Moraes, A. G. Ortiz, M. Glesner, and R. A. L. Reis, "Evaluating the impact of data encoding techniques on the power consumption in networks-on-chip," in Proc. IEEE Comput. Soc. Annu. Symp. Emerging VLSI Technol. Archit., 2006, Art. no. 2
64. A. Berman, R. Ginosar, and I. Keider, "Order is power: Selective Packet Interleaving for energy efficient Networks-on-Chip," in Proc. 18th IEEE/IFIP Int. Conf. VLSI Syst. Chip, 2010, pp. 37-42
65. M. Palesi, G. Ascia, F. Fazzino, and V. Catania, "Data encoding schemes in networks on chip," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 30, no. 5, pp. 774-786, May 2011
66. M. Taassori, M. Taassori, and S. Uysal, "MFLP: A low power encoding for on chip networks," Int. J. DAES, vol. 20, no. 3, pp. 191-210, 2016
67. A. Sheibanyrad, A. Greiner, and I. Miro-Panades, "Multisynchronous, and fully asynchronous NoCs for GALS architectures," IEEE Des. Test Comput., vol. 25, no. 6, pp. 572-580, Nov./Dec. 2008
68. E. Rijpkema, et al., "Trade-offs in the design of a router with both guaranteed, and best-effort services for networks on chip," in Proc. Des. Autom. Test Europe Conf. Exhib., 2003, pp. 350-355
69. L. S. Indrusiak, J. Harbin, and O.M. Dos Santos, "Fast simulation of networks-on-chip with priority-preemptive arbitration," ACM Trans.Des. Autom. Electron. Syst., vol. 20, no. 4, pp. 56: 1-56: 22, 2015
70. L. Ost, G. Guindani, L. S. Indrusiak, C. Reinbrecht, T. Raupp, and F. Moraes, "A high abstraction high accuracy power estimation model for networks-on-chip," in Proc. 22nd Annu. Symp. Integr. Circuits Syst. Des. Chip Dunes, 2009, Art. no. 31
71. K. Heid, H. Ying, C. Hochberger, and K. Hofmann, "LatEst: Latency estimation, and high speed evaluation for wormhole switched networks-on-chip," in Proc. 9th Int. Symp. Reconfigurable Commun.-Centric Syst. Chip., 2014, pp. 1-7
72. A. Butko, et al., "A Trace-driven approach for fast, and accurate simulation of Manycore architectures," in Proc. 20th Asia South Pacific Des. Autom. Conf., 2015, pp. 707-712
73. J. Xu, and D. L. Parnas, "Priority scheduling versus pre-run-time scheduling," Real-Time Syst., vol. 18, no. 1, pp. 7-23, 2000
74. J. Diemer, and R. Ernst, "A link arbitration scheme for quality of service in a latency-optimized network-on-chip," in Proc. Des. Autom. Test Europe Conf. Exhib., 2009, pp. 574-577
75. C. Zeferino, and A. Susin, "SoCIN: A parametric, and scalable network-on-chip," in Proc. 16th Symp. Integr. Circuits Syst. Des., 2003, 169-174
76. F. Moraes, N. Calazans, A. Mello, L.Möller, and L. Ost, "Hermes: an infrastructure for low area overhead packet-switching networks on chip," Integr. VLSI J., vol. 38, no. 1, pp. 69-93, 2004
77. K. Goossens, J. Dielissen, O. Gangwal, S. Pestana, A. Radulescu, and E. Rijpkema, "A design flow for application-specific networks on chip with guaranteed performance to accelerate SOC design, and verification," in Proc. Des. Autom. Test Europe, 2005, pp. 1182-1187
78. A. Hansson, M. Coenen, and K. Goossens, "Undisrupted qualityof-service during reconfiguration of multiple applications in networks on chip," in Proc. Des. Autom. Test Europe Conf. Exhib., 2007, pp. 1-6
79. A. Hansson, K. Goossens, and A. Radulescu, "A unified approach to mapping, and routing on a network-on-chip for both best-effort, and guaranteed service traffic," VLSI Design, vol. 2007, 2007, Art. no. 68432
80. R. B. Sørensen, J. Sparsø, M. R. Pedersen, and J. Højgaard, "A metaheuristic scheduler for time division multiplexed networkson-chip," in Proc. IEEE 17th Int. Symp. Object/Component/Service-Oriented Real-Time Distrib. Comput., 2014, pp. 309-316
81. H. Zhang, "Service disciplines for guaranteed performance service in packet-switching networks," Proc. IEEE, vol. 83, no. 10, pp. 1374-1396, Oct. 1995
82. N. Agarwal, T. Krishna, L.-S. Peh, and N. Jha, "GARNET: Adetailed on-chip network model inside a full-system simulator," in Proc. IEEE Int. Symp. Performance Anal. Syst. Softw., 2009, pp. 33-32
83. Z. Shi, A. Burns, and L. Indrusiak, "Schedulability analysis for real time on-chip communication with wormhole switching," Int. J. Embedded Real-Time Commun. Syst., vol. 1, no. 2, pp. 1-22, 2010
84. M. Bekooij, et al., "Dataflow analysis for real-time embedded multiprocessor system design," in Dynamic, and Robust Streaming in, and Between Connected Consumer-Electronic Devices. Dordrecht, Netherlands: Springer , 2005, pp. 81-108
85. Y. Qian, Z. Lu, and W. Dou, "Analysis of worst-case delay bounds for best-effort communication in wormhole networkson-chip," in Proc. 3rd ACM/IEEE Int. Symp. Netw. Chip, 2009, pp. 44-53
86. B. Nikolic, P. M. Yomsi, and S. M. Petters, "Worst-case communication delay analysis for NoC-based many-cores using a limited migrative model," J. Signal Process. Syst., vol. 84, no. 1, pp. 25-46, 2015
87. E. A. Rambo, and R. Ernst, "Worst-case communication time analysis of networks-on-chip with shared virtual channels," in Proc. Des. Autom. Test Europe Conf. Exhib., 2015, pp. 537-542
88. C. Bienia, S. Kumar, J. S. Singh, and K. Li, "ThePARSECbenchmark suite: Characterization, and architectural implications," in Proc. 17th Int. Conf. Parallel Archit. Compilation techn., 2008, pp. 72-81
89. S. Che, et al., "Rodinia: A benchmark suite for heterogeneous computing," in Proc. IEEE Int. Symp. Workload Characterization, 2009, pp. 44-54
90. A. Bakhoda, G. Yuan, W. Fung, H. Wong, and T. Aamodt, "Analyzing CUDA workloads using a detailed GPU simulator," in Proc. IEEE Int. Symp. Performance Anal. Syst. Softw., 2009, pp. 163-174
91. V. Aslot, M. J. Domeika, R. Eigenmann, G. Gaertner, W. B. Jones, and B. Parady, "SPEComp: A new benchmark suite for measuring parallel computer performance," in Proc. Int. Workshop OpenMP Appl. Tools: OpenMP Shared Memory Parallel Program., 2001, pp. 1-10
92. S. Woo, M. Ohara, E. Torrie, J. Singh, and A. Gupta, "The SPLASH-2 programs: Characterization, and methodological considerations," in Proc. 22nd Annu. Int. Symp. Comput. Archit., 1995, pp. 24-36
93. N. Hardavellas, M. Ferdman, B. Falsafi, and A. Ailamaki, "Toward dark silicon in servers," IEEE Micro, vol. 31, no. 4, pp. 6-15, Jul. 2011
94. T. Ye, L. Benini, and G. De Micheli, "Analysis of power consumption on switch fabrics in network routers," in Proc. 39th Annu. Des. Autom. Conf., 2002, pp. 524-529
95. A. Kahng, B. Li, L.-S. Peh, and K. Samadi, "ORION 2.0: A fast, and accurate NoC power, and area model for early-stage design space exploration," in Proc. Conf. Des. Autom. Test Europe, 2009, pp. 423-428
96. J. Fong, S. Nath, A. B. Kahng, and B. Lin, "ORION3.0: A powerperformance simulator for interconnection networks." (2012). [Online]. Available: http://vlsicad.ucsd.edu/ORION3
97. N. Jiang, et al., "A detailed, and flexible cycle-accurate networkon-chip simulator," in Proc. IEEE Int. Symp. Performance Anal. Syst. Softw., 2013, pp. 86-96
98. OPNET Technologies. (2000). [Online]. Available: http://www. opnet.com
99. C. Sun, et al., "DSENT-A Tool Connecting Emerging Photonics with Electronics for Opto-Electronic Networks-on-Chip Modeling," in Proc. IEEE/ACM 6th Int. Symp. Netw. Chip, 2012, pp. 201-210
100. "International Technology Roadmap for Semiconductors," 2012. [Online]. Available: http://www.itrs.net/reports.html
101. E. Salminen, E. Kulmala, and T. D. Hämäläinen, "On networkon-chip comparison," in Proc. 10th Euromicro Conf. Dig. Syst. Des. Archit. Methods Tools, 2007, pp. 503-510
102. J. Sparsø, E. Kasapaki, and M. Schoeberl, "An Area-efficient Network Interface for a TDM-based Network-on-Chip," in Proc. Des. Autom. Test Europe Conf. Exhib., 2013, pp. 1044-1047
103. S. Hesham, D. Goehringer, and M. A. Abdel-Ghany, "ARTNoCs: An evaluation framework for hardware architectures of realtime NoCs," in Proc. IEEE Int. Parallel Distrib. Process. Symp. Workshops, 2016, pp. 259-264
104. H. Bokhari, H. Javaid, M. Shafique, J. Henkel, and S. Parameswaran, "Malleable NoC: Dark silicon inspired adaptable Network-on-Chip," in Proc. Des. Autom. Test Europe Conf. Exhib., 2015, pp. 1245-1248