LatEst: Latency estimation and high speed evaluation for wormhole switched Networks-on-Chip

2014 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip, ReCoSoC 2014

Volumn , Issue , 2014, Pages

  Heid, Kris ^a   Ying, Haoyuan ^b   Hochberger, Christian ^a   Hofmann, Klaus ^b  

^a Computer Systems Group ^*  (Germany)

^b DARMSTADT UNIVERSITY OF TECHNOLOGY   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

MICROPROCESSOR CHIPS; OPTIMIZATION;

ABSTRACT MODELING; DATA STREAM; LATENCY ANALYSIS; LATENCY ESTIMATION; NETWORKS ON CHIPS; OPTIMIZATION PROBLEMS; PERFORMANCE ESTIMATION; SENDING RATE;

NETWORK-ON-CHIP;

EID: 84905671086     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ReCoSoC.2014.6861335     Document Type: Conference Paper

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