-
2
-
-
84859967419
-
SPIN: A scalable, packet switched, on-chip micro-network
-
Mar
-
A. Adriahantenaina et al., "SPIN: a scalable, packet switched, on-chip micro-network," in DATE, Mar. 2003, pp. 70-73.
-
(2003)
DATE
, pp. 70-73
-
-
Adriahantenaina, A.1
-
3
-
-
33746343324
-
On the credibility of manet simulations
-
Jul
-
T. Andel and A. Yasinsac, "On the credibility of manet simulations," IEEE Computer, vol. 39, no. 7, pp. 48-54, Jul. 2006.
-
(2006)
IEEE Computer
, vol.39
, Issue.7
, pp. 48-54
-
-
Andel, T.1
Yasinsac, A.2
-
4
-
-
34047170421
-
Contrasting a NoC and a traditional interconnect fabric with layout awareness
-
Mar
-
F. Angiolini et al., "Contrasting a NoC and a traditional interconnect fabric with layout awareness," in DATE, Mar. 2006, pp. 1-6.
-
(2006)
DATE
, pp. 1-6
-
-
Angiolini, F.1
-
5
-
-
35048885539
-
Network-on-chip for reconfigurable systems: From high-level design down to implementation
-
T. Bartic et al., "Network-on-chip for reconfigurable systems: From high-level design down to implementation," in FPL, 2004, pp. 637-647.
-
(2004)
FPL
, pp. 637-647
-
-
Bartic, T.1
-
6
-
-
23744439113
-
Topology adaptive network-on-chip design and implementation
-
Jul
-
_, "Topology adaptive network-on-chip design and implementation," IEE Proc. Comput. Digit. Tech., vol. 152, no. 4, pp. 467-472, Jul. 2005.
-
(2005)
IEE Proc. Comput. Digit. Tech
, vol.152
, Issue.4
, pp. 467-472
-
-
Bartic, T.1
-
7
-
-
0036149420
-
Networks on chips: A new SoC paradigm
-
Jan
-
L. Benini and G. de Micheli, "Networks on chips: A new SoC paradigm," IEEE Computer, vol. 35, no. 1, pp. 70-78, Jan. 2002.
-
(2002)
IEEE Computer
, vol.35
, Issue.1
, pp. 70-78
-
-
Benini, L.1
de Micheli, G.2
-
9
-
-
14844365666
-
Noc synthesis flow for customized domain specific multiprocessor systems-on-chip
-
Feb
-
D. Bertozzi et al., "Noc synthesis flow for customized domain specific multiprocessor systems-on-chip," IEEE Trans. Parallel and Distributed Systems, vol. 16, no. 2, pp. 113-129, Feb. 2005.
-
(2005)
IEEE Trans. Parallel and Distributed Systems
, vol.16
, Issue.2
, pp. 113-129
-
-
Bertozzi, D.1
-
10
-
-
84941344008
-
Interfacing cores with on-chip packet-switched networks
-
Jan
-
P. Bhojwani and R. Mahapatra, "Interfacing cores with on-chip packet-switched networks," in VLSI design, Jan. 2003, pp. 382-387.
-
(2003)
VLSI design
, pp. 382-387
-
-
Bhojwani, P.1
Mahapatra, R.2
-
11
-
-
33745800231
-
-
T. Bjerregaard and S. Mahadevan, A survey of research and practices of network-on-chip, ACM Computing Surveys, 38, no. 1, p. article No. 1, 2006.
-
T. Bjerregaard and S. Mahadevan, "A survey of research and practices of network-on-chip," ACM Computing Surveys, vol. 38, no. 1, p. article No. 1, 2006.
-
-
-
-
12
-
-
9544239365
-
Cost considerations in network on chip
-
Oct
-
E. Bolotin et al., "Cost considerations in network on chip," Integration, the VLSI Journal, vol. 38, no. 1, pp. 19-42, Oct. 2004.
-
(2004)
Integration, the VLSI Journal
, vol.38
, Issue.1
, pp. 19-42
-
-
Bolotin, E.1
-
13
-
-
34247201233
-
Design space exploration on heterogeneous network-on-chip
-
May
-
R. Cardoso et al., "Design space exploration on heterogeneous network-on-chip," in ISCAS, May 2005, pp. 428-431.
-
(2005)
ISCAS
, pp. 428-431
-
-
Cardoso, R.1
-
14
-
-
34547211508
-
Evaluation and design trade-offs between circuit-switched and packet-switched NOCs for application-specific SOCs
-
Jul
-
K.-C. Chang, J.-S. Shen, and T.-F. Chen, "Evaluation and design trade-offs between circuit-switched and packet-switched NOCs for application-specific SOCs," in DAC, Jul. 2006, pp. 143-148.
-
(2006)
DAC
, pp. 143-148
-
-
Chang, K.-C.1
Shen, J.-S.2
Chen, T.-F.3
-
15
-
-
41549142400
-
A SystemC test environment for SPIN network
-
Jun
-
H. Charlery and A. Greiner, "A SystemC test environment for SPIN network," in MIXDES, Jun. 2006, pp. 449-453.
-
(2006)
MIXDES
, pp. 449-453
-
-
Charlery, H.1
Greiner, A.2
-
16
-
-
0027228834
-
Architectural requirements of parallel scientific applications with explicit communication
-
R. Cypher, A. Ho, S. Konstantinidou, and P. Messian, "Architectural requirements of parallel scientific applications with explicit communication," in ISCA, 1993, pp. 2-13.
-
(1993)
ISCA
, pp. 2-13
-
-
Cypher, R.1
Ho, A.2
Konstantinidou, S.3
Messian, P.4
-
18
-
-
0034848112
-
Route packets, not wires: On-chip interconnection networks
-
W. Dally and B. Towles, "Route packets, not wires: on-chip interconnection networks," in DAC, 2001, pp. 684-689.
-
(2001)
DAC
, pp. 684-689
-
-
Dally, W.1
Towles, B.2
-
20
-
-
34047168005
-
Flexible MPSoC platform with fast interconnect exploration for optimal system performance for a specific application
-
Mar
-
F. Dumitrascu et al., "Flexible MPSoC platform with fast interconnect exploration for optimal system performance for a specific application," in DATE, Mar. 2006, pp. 1-6.
-
(2006)
DATE
, pp. 1-6
-
-
Dumitrascu, F.1
-
22
-
-
2342622625
-
On-chip networks: A scalable, communication-centric embedded system design paradigm
-
Jan
-
J. Henkel, W. Wolf, and S. Chakradhar, "On-chip networks: a scalable, communication-centric embedded system design paradigm," in VLSI, Jan. 2004, pp. 845-851.
-
(2004)
VLSI
, pp. 845-851
-
-
Henkel, J.1
Wolf, W.2
Chakradhar, S.3
-
23
-
-
79960683260
-
A flexible circuit switched NOC for FPGA based systems
-
C. Hilton and B. Nelson, "A flexible circuit switched NOC for FPGA based systems," in FPL, 2005, pp. 24-26.
-
(2005)
FPL
, pp. 24-26
-
-
Hilton, C.1
Nelson, B.2
-
24
-
-
84962259776
-
System-level point-to-point communication synthesis using floorplanning information
-
Jan
-
J. Hu, Y. Deng, and R. Marculescu, "System-level point-to-point communication synthesis using floorplanning information," in ASPDAC/VLSI, Jan. 2002, pp. 573-579.
-
(2002)
ASPDAC/VLSI
, pp. 573-579
-
-
Hu, J.1
Deng, Y.2
Marculescu, R.3
-
25
-
-
0042111484
-
-
A. Jantsch and H. Tenhunen, Eds, Dordrecht, The Netherlands: Kluwer Academic Publishers
-
A. Jantsch and H. Tenhunen, Eds., Networks on Chip. Dordrecht, The Netherlands: Kluwer Academic Publishers, 2003.
-
(2003)
Networks on Chip
-
-
-
26
-
-
0036760592
-
An interconnect architecture for networking systems on chips
-
Sep.-Oct
-
F. Karim, A. Nguyen, and S. Dey, "An interconnect architecture for networking systems on chips," IEEE Micro, vol. 22, no. 5, pp. 36-45, Sep.-Oct. 2002.
-
(2002)
IEEE Micro
, vol.22
, Issue.5
, pp. 36-45
-
-
Karim, F.1
Nguyen, A.2
Dey, S.3
-
27
-
-
44149127082
-
Energy and latency evaluation of NoC topologies
-
May
-
M. Kreutz et al., "Energy and latency evaluation of NoC topologies," in ISCAS, vol. 6, May 2005, pp. 5866-5869.
-
(2005)
ISCAS
, vol.6
, pp. 5866-5869
-
-
Kreutz, M.1
-
28
-
-
84966331156
-
Communication architectures for system-on-chip
-
M. E. Kreutz et al., "Communication architectures for system-on-chip," in SBCCI, 2001, pp. 14-19.
-
(2001)
SBCCI
, pp. 14-19
-
-
Kreutz, M.E.1
-
29
-
-
0037656855
-
A network on chip architecture and design methodology
-
April
-
S. Kumar et al., "A network on chip architecture and design methodology," in VLSI, April 2002, pp. 105-112.
-
(2002)
VLSI
, pp. 105-112
-
-
Kumar, S.1
-
30
-
-
0034995968
-
Evaluation of the traffic-performance characteristics of system-on-chip communication architectures
-
K. Lahiri, A. Raghunathan, and S. Dey, "Evaluation of the traffic-performance characteristics of system-on-chip communication architectures," in Conference on VLSI design, 2001, pp. 29-35.
-
(2001)
Conference on VLSI design
, pp. 29-35
-
-
Lahiri, K.1
Raghunathan, A.2
Dey, S.3
-
31
-
-
0037743915
-
Comparison of synthesized bus and crossbar interconnection architectures
-
May
-
V. Lahtinen et al., "Comparison of synthesized bus and crossbar interconnection architectures," in ISCAS, vol. 5, May 2003, pp. 433-436.
-
(2003)
ISCAS
, vol.5
, pp. 433-436
-
-
Lahtinen, V.1
-
32
-
-
33748417105
-
Design space exploration and prototyping for on-chip multimedia applications
-
Jul
-
H. G. Lee et al., "Design space exploration and prototyping for on-chip multimedia applications," in DAC, Jul. 2006, pp. 137-142.
-
(2006)
DAC
, pp. 137-142
-
-
Lee, H.G.1
-
33
-
-
33645011974
-
Low-power network-on-chip for high-performance soc design
-
Feb
-
K. Lee, S.-J. Lee, and H.-J. Yoo, "Low-power network-on-chip for high-performance soc design," IEEE Trans. VLSI Syst., vol. 14, no. 2, pp. 148-160, Feb. 2006.
-
(2006)
IEEE Trans. VLSI Syst
, vol.14
, Issue.2
, pp. 148-160
-
-
Lee, K.1
Lee, S.-J.2
Yoo, H.-J.3
-
34
-
-
3142720340
-
An architecture and compiler for scalable on-chip communication
-
J. Liang et al., "An architecture and compiler for scalable on-chip communication," IEEE Trans. VLSI Syst., vol. 12, no. 7, pp. 711-726, 2004.
-
(2004)
IEEE Trans. VLSI Syst
, vol.12
, Issue.7
, pp. 711-726
-
-
Liang, J.1
-
35
-
-
47749114449
-
Self-timed ring architecture for SOC applications
-
Sep
-
P. Liljeberg, J. Plosila, and J. Isoaho, "Self-timed ring architecture for SOC applications," in SOCC, Sep. 2003, pp. 359-362.
-
(2003)
SOCC
, pp. 359-362
-
-
Liljeberg, P.1
Plosila, J.2
Isoaho, J.3
-
36
-
-
3042511814
-
Analyzing on-chip communication in a MPSoC environment
-
Feb
-
M. Loghi et al., "Analyzing on-chip communication in a MPSoC environment," in DATE, Feb. 2004, pp. 752-757.
-
(2004)
DATE
, pp. 752-757
-
-
Loghi, M.1
-
37
-
-
0347409249
-
Samba-bus: A high performance bus architecture for system-on-chips
-
Nov
-
R. Lu and C.-K. Koh, "Samba-bus: a high performance bus architecture for system-on-chips," in ICCAD, Nov. 2003, pp. 8-12.
-
(2003)
ICCAD
, pp. 8-12
-
-
Lu, R.1
Koh, C.-K.2
-
38
-
-
33750928209
-
Evaluation of on-chip networks using deflection routing
-
May
-
Z. Lu, M. Zhong, and A. Jantsch, "Evaluation of on-chip networks using deflection routing," in GLSVLSI, May 2006, pp. 296-301.
-
(2006)
GLSVLSI
, pp. 296-301
-
-
Lu, Z.1
Zhong, M.2
Jantsch, A.3
-
39
-
-
9544237156
-
Hermes: An infrastructure for low area overhead packet-switching networks on chip
-
Oct
-
F. Moraes et al., "Hermes: an infrastructure for low area overhead packet-switching networks on chip," Integration, the VLSI Journal, vol. 38, no. 1, pp. 69-93, Oct. 2004.
-
(2004)
Integration, the VLSI Journal
, vol.38
, Issue.1
, pp. 69-93
-
-
Moraes, F.1
-
40
-
-
36849045881
-
An initiatie towards open network-on-chip benchmarks
-
NoC Benchmark Workgroup, white paper, OCP-IP, Online
-
NoC Benchmark Workgroup, "An initiatie towards open network-on-chip benchmarks," white paper, OCP-IP, [Online] http://www.ocpip.org/socket/ whitepapers/NoC-Benchmarks-WhitePaper-15.pdf, 2007.
-
(2007)
-
-
-
41
-
-
21244503275
-
-
J. Nurmi, H. Tenhunen, J. Isoaho, and A. Jantsch, Eds, Dordrecht, The Netherlands: Kluwer Academic Publishers
-
J. Nurmi, H. Tenhunen, J. Isoaho, and A. Jantsch, Eds., Interconnect-Centric Design for Advanced SoC and NoC. Dordrecht, The Netherlands: Kluwer Academic Publishers, 2004.
-
(2004)
Interconnect-Centric Design for Advanced SoC and
-
-
-
42
-
-
27644494723
-
Key research problems in noc design: A holistic perspective
-
U. Y. Ogras, J. Hu, and R. Marculescu, "Key research problems in noc design: a holistic perspective," in CODES, 2005, pp. 69-75.
-
(2005)
CODES
, pp. 69-75
-
-
Ogras, U.Y.1
Hu, J.2
Marculescu, R.3
-
43
-
-
34047150878
-
Communication architecture optimization: Making the shortest path shorter in regular networks-on-chip
-
Mar
-
U. Ogras et al., "Communication architecture optimization: making the shortest path shorter in regular networks-on-chip," in DATE, Mar. 2006.
-
(2006)
DATE
-
-
Ogras, U.1
-
44
-
-
0038420731
-
Design of a switch for network on chip applications
-
P. P. Pande et al., "Design of a switch for network on chip applications," in ISCAS, 2003, pp. 217-220.
-
(2003)
ISCAS
, pp. 217-220
-
-
Pande, P.P.1
-
45
-
-
24144461667
-
Performance evaluation and design trade-offs for network-on-chip interconnect architectures
-
Aug
-
P. Pande et al., "Performance evaluation and design trade-offs for network-on-chip interconnect architectures," IEEE Trans. Computers, vol. 54, no. 8, pp. 1025-1040, Aug. 2005.
-
(2005)
IEEE Trans. Computers
, vol.54
, Issue.8
, pp. 1025-1040
-
-
Pande, P.1
-
46
-
-
34547986791
-
A high level power model for the Nostrum
-
Aug
-
S. Penolazzi and A. Jantsch, "A high level power model for the Nostrum NoC," in DSD, Aug. 2006, pp. 673-676.
-
(2006)
DSD
, pp. 673-676
-
-
Penolazzi, S.1
Jantsch, A.2
-
47
-
-
84949231249
-
Towards efficient design space exploration of heterogeneous embedded media systems
-
A. D. Pimentel et al., "Towards efficient design space exploration of heterogeneous embedded media systems," in SAMOS, 2002, pp. 57-63.
-
(2002)
SAMOS
, pp. 57-63
-
-
Pimentel, A.D.1
-
48
-
-
11844249902
-
An efficient on-chip NI offering guaranteed services, shared-memory abstraction, and flexible network configuration
-
Jan
-
A. Radulescu et al., "An efficient on-chip NI offering guaranteed services, shared-memory abstraction, and flexible network configuration," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 1, pp. 4-17, Jan. 2005.
-
(2005)
IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems
, vol.24
, Issue.1
, pp. 4-17
-
-
Radulescu, A.1
-
49
-
-
33748554106
-
A hybrid SoC interconnect with dynamic TDMA-based transaction-less buses and on-chip networks
-
Jan
-
T. Richardson et al., "A hybrid SoC interconnect with dynamic TDMA-based transaction-less buses and on-chip networks," in VLSI design, Jan. 2006.
-
(2006)
VLSI design
-
-
Richardson, T.1
-
50
-
-
8344242181
-
Automated bus generation for multiprocessor SoC design
-
Nov
-
K. K. Ryu and V. J. Mooney III, "Automated bus generation for multiprocessor SoC design," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 23, no. 11, pp. 1531-1549, Nov. 2004.
-
(2004)
IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems
, vol.23
, Issue.11
, pp. 1531-1549
-
-
Ryu, K.K.1
Mooney III, V.J.2
-
51
-
-
0038760864
-
Buffer implementation for Proteo network-on-chip
-
I. Saastamoinen, M. Alho, and J. Nurmi, "Buffer implementation for Proteo network-on-chip," in ISCAS, 2003, pp. 113-116.
-
(2003)
ISCAS
, pp. 113-116
-
-
Saastamoinen, I.1
Alho, M.2
Nurmi, J.3
-
52
-
-
34248522579
-
Benchmarking mesh and hierarchical bus networks in system-on-chip context
-
Aug
-
E. Salminen et al., "Benchmarking mesh and hierarchical bus networks in system-on-chip context," Journal of System Architectures (in press), vol. 53, no. 8, pp. 477-488, Aug. 2007.
-
(2007)
Journal of System Architectures (in press)
, vol.53
, Issue.8
, pp. 477-488
-
-
Salminen, E.1
-
53
-
-
50049127075
-
The impact of communication on the scalability of the data-parallel video encoder on MPSoC
-
Nov
-
E. Salminen, T. Kangas, and T. Hämäläinen, "The impact of communication on the scalability of the data-parallel video encoder on MPSoC," in Intl. Symposium on Soc, Nov. 2006, pp. 191-194.
-
(2006)
Intl. Symposium on Soc
, pp. 191-194
-
-
Salminen, E.1
Kangas, T.2
Hämäläinen, T.3
-
54
-
-
33847226043
-
Evaluating application mapping using network simulation
-
Nov
-
T. Salminen and J.-P. Soininen, "Evaluating application mapping using network simulation," in Intl. Symposium on Soc, Nov. 2003, pp. 27-30.
-
(2003)
Intl. Symposium on Soc
, pp. 27-30
-
-
Salminen, T.1
Soininen, J.-P.2
-
55
-
-
34547339205
-
On a design of crossroad switches for low-power on-chip communication architectures
-
May
-
J.-S. Shen, K.-C. Chang, and T.-F. Chen, "On a design of crossroad switches for low-power on-chip communication architectures," in ISCAS, May 2006.
-
(2006)
ISCAS
-
-
Shen, J.-S.1
Chang, K.-C.2
Chen, T.-F.3
-
56
-
-
84891462850
-
A statistical traffic model for on-chip interconnection networks
-
V. Soteriou, H. Wang, and L.-S. Peh, "A statistical traffic model for on-chip interconnection networks," in MASCOTS, 2006, pp. 104-116.
-
(2006)
MASCOTS
, pp. 104-116
-
-
Soteriou, V.1
Wang, H.2
Peh, L.-S.3
-
57
-
-
26444519559
-
Evaluating NoC communication backbones with simulation
-
R. Thid, M. Millberg, and A. Jantsch, "Evaluating NoC communication backbones with simulation," in Norchip, 2003, pp. 27-30.
-
(2003)
Norchip
, pp. 27-30
-
-
Thid, R.1
Millberg, M.2
Jantsch, A.3
-
58
-
-
34547983104
-
Flexible bus and NoC performance analysis with configurable synthetic workloads
-
R. Thid, I. Sander, and A. Jantsch, "Flexible bus and NoC performance analysis with configurable synthetic workloads," in DSD, 2006, pp. 681-688.
-
(2006)
DSD
, pp. 681-688
-
-
Thid, R.1
Sander, I.2
Jantsch, A.3
-
60
-
-
84949672053
-
Networks on silicon: Blessing or night-mare?
-
Sep
-
P. Wielage and K. Goossens, "Networks on silicon: blessing or night-mare?" in DSD, Sep. 2002, pp. 196-200.
-
(2002)
DSD
, pp. 196-200
-
-
Wielage, P.1
Goossens, K.2
-
61
-
-
41349095609
-
Switched interconnect for system-on-a-chip designs
-
Oct
-
D. Wiklund and D. Liu, "Switched interconnect for system-on-a-chip designs," in IP2000, Oct. 2000, pp. 198-192.
-
(2000)
IP
, vol.2000
, pp. 198-192
-
-
Wiklund, D.1
Liu, D.2
-
62
-
-
33746316540
-
An energy-efficient reconfigurable circuit-switched network-on-chip
-
Apr
-
P. Wolkotte et al., "An energy-efficient reconfigurable circuit-switched network-on-chip," in IPDPS, Apr. 2005, p. 155a.
-
(2005)
IPDPS
-
-
Wolkotte, P.1
-
63
-
-
33847228171
-
Methodology for design, modeling, and analysis of networks-on-chip
-
May
-
J. Xu et al., "Methodology for design, modeling, and analysis of networks-on-chip," in ISCAS, May 2005, pp. 1778-1781.
-
(2005)
ISCAS
, pp. 1778-1781
-
-
Xu, J.1
-
64
-
-
1242309793
-
Packetization and routing analysis of on-chip multiprocessor
-
Feb
-
T. Ye, L. Benini, and G. de Micheli, "Packetization and routing analysis of on-chip multiprocessor," Journal of System Architecture, vol. 50, pp. 81-104, Feb. 2004.
-
(2004)
Journal of System Architecture
, vol.50
, pp. 81-104
-
-
Ye, T.1
Benini, L.2
de Micheli, G.3
-
65
-
-
47749106715
-
Models for communication tradeoffs on systems-on-chip
-
Oct
-
C. A. Zeferino et al., "Models for communication tradeoffs on systems-on-chip," in IP based design, Oct. 2002, pp. 394-400.
-
(2002)
IP based design
, pp. 394-400
-
-
Zeferino, C.A.1
-
66
-
-
34548342553
-
A study on communication issues for system-on-chip
-
Sep
-
_, "A study on communication issues for system-on-chip," in SBCCI, Sep. 2002, pp. 121-126.
-
(2002)
SBCCI
, pp. 121-126
-
-
Zeferino, C.A.1
-
67
-
-
85008008992
-
Interconnect architecture exploration for low-energy reconfigurable single-chip DSPs
-
Orlando, Florida, USA
-
H. Zhang et al., "Interconnect architecture exploration for low-energy reconfigurable single-chip DSPs," in Workshop on VLSI, Orlando, Florida, USA, 1999, pp. 2-8.
-
(1999)
Workshop on VLSI
, pp. 2-8
-
-
Zhang, H.1
|