GARNET: A detailed on-chip network model inside a full-system simulator

ISPASS 2009 - International Symposium on Performance Analysis of Systems and Software

Volumn , Issue , 2009, Pages 33-42

  Agarwal, Niket ^a   Krishna, Tushar ^a   Peh, Li Shiuan ^a   Jha, Niraj K ^a  

^a Princeton University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALLOCATORS; CHIP MULTIPROCESSOR; CRITICAL PARTS; CROSSBAR SWITCH; CYCLE ACCURATE; DESIGN PROPOSAL; FULL SYSTEM SIMULATORS; FULL-SYSTEM SIMULATION; GLOBAL WIRES; INPUT BUFFERS; INTERCONNECT POWER; MEMORY HIERARCHY; MEMORY SYSTEMS; MICROPROCESSOR DESIGNS; ON CHIP COMMUNICATION; ON-CHIP NETWORKS; POTENTIAL IMPACTS; PROCESSING CORE; RUNTIMES; SIMPLE NETWORKS; SINGLE CYCLE; SYSTEM BEHAVIORS; SYSTEM EVALUATION; TIMING MODELS; UNIPROCESSORS; VIRTUAL CHANNELS;

COMMUNICATION CHANNELS (INFORMATION THEORY); COMPUTER SOFTWARE; DESIGN; ELECTRIC NETWORK TOPOLOGY; ELECTRON MULTIPLIERS; EMBEDDED SYSTEMS; GARNETS; INTERCONNECTION NETWORKS; MICROPROCESSOR CHIPS; NANOTECHNOLOGY; ROUTERS; SILICATE MINERALS; SIMULATORS;

ARTS COMPUTING;

EID: 70049105948     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISPASS.2009.4919636     Document Type: Conference Paper

References (31)

1. PoPNet. http://www.princeton.edu/edu/̃lshang/popnet.html.
2. A. R. Alameldeen and D. A. Wood. IPC considered harmful for multiprocessor workloads. IEEE Micro, 26(4):8?17, 2006.
3. Arvind, K. Asanovic, D. Chiou, J. C. Hoe, C. Kozyrakis, S.- L. Lu, M. Oskin, D. Patterson, J. Rabaey, and J. Wawrzynek. RAMP: Research accelerator for multiple processors - A community vision for a shared experimental parallel HW/SW platform. Technical Report UCB/CSD-05-1412, EECS, Dept. Univ. of California, Berkeley, Sept. 2005.
4. T. Austin, E. Larson, and D. Ernst. Simplescalar: An infrastructure for computer system modeling. Computer, 35(2):59-67, Feb. 2002.
5. H. Cain, K. Lepak, B. Schwarz, and M. H. Lipasti. Precise and accurate processor simulation. In Proc. Wkshp. Computer Architecture Evaluation using Commercial Workloads, 2002.
6. M. F. Chang, J. Cong, A. Kaplan, C. Liu, M. Naik, J. Premkumar, G. Reinman, E. Socher, and S.-W. Tam. Power reduction of CMP communication networks via RF-interconnects. In Proc. Int. Symp. Microarchitecture, Nov. 2008.
7. X.-N. Chen and L.-S. Peh. Leakage power modeling and optimization of interconnection networks. In Proc. Int. Symp. Low Power Electronics and Design, pages 90?95, Aug. 2003.
8. D. E. Culler, J. P. Singh, and A. Gupta. Parallel Computer Architecture: A Hardware/Software Approach. Morgan Kaufmann, 1998.
9. W. J. Dally. Virtual channel flow control. IEEE Trans. Parallel and Distributed Systems, 3(2):194?205, Mar. 1992.
10. W. J. Dally and B. Towles. Principles and Practices of Interconnection Networks. Morgan Kaufmann Pub., San Francisco, CA, 2003.
11. J. Emer, P. Ahuja, E. Borch, A. Klauser, C.-K. Luk, S. Manne, S. S. Mukherjee, H. Patil, S. Wallace, N. Binkert, R. Espasa, and T. Juan. Asim: A performance model framework. Computer, 35(2):68?76, 2002.
12. J. Flich, A. Mejia, P. Lopez, and J. Duato. Region-based routing: An efficient routing mechanism to tackle unreliable hardware in network on chips. In Proc. Int. Symp. Networks-on-Chip, pages 183?194, May 2007.
13. IBM. http://www-128.ibm.com/developerworks/power/library/pa-expert1.html.
14. Intel. From a few cores to many: A tera-scale computing research overview. http://download.intel.com/research/platform/terascale/terascale- overview-paper.pdf, 2006.
15. N. E. Jerger, L.-S. Peh, and M. Lipasti. Virtual circuit tree multicasting: A case for on-chip hardware multicast support. In Proc. Int. Symp. Computer Architecture, June 2008.
16. C. Kim, D. Burger, and S. W. Keckler. An adaptive, non- uniform cache structure for wire- delay dominated on-chip caches. In Proc. Int. Conf. Architectural Support for Programming Languages and Operating Systems, Oct. 2002.
17. J. Kim, J. Balfour, andW. J. Dally. Flattened butterfly topologyfor on-chip networks. In Proc. Int. Symp. Microarchitecture, Nov. 2007.
18. J. S. Kim, M. B. Taylor, J. Miller, and D. Wentzlaff. Energy characterization of a tiled architecture processor with on-chip networks. In Proc. Int. Symp. Low Power Electronics and Design, pages 424-427, Aug. 2003
19. A. Kumar, L.-S. Peh, P. Kundu, and N. K. Jha. Express virtual channels: Towards the ideal interconnection fabric. In Proc. Int. Symp. Computer Architecture (and IEEE Micro Top Picks 2008), June 2007.
20. M. Martin, D. Sorin, B. Beckmann, M. Marty, M. Xu, A. Alameldeen, K. Moore, M. Hill, and D. A. Wood. Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset. Computer Architecure News, 2005.
21. J. Moses, R. Illikkal, R. Iyer, R. Huggahalli, and D. Newell. Aspen: Towards effective simulation of threads and engines in evolving platforms. In Proc. Int. Symp. Modeling, Analysis, and Simulation of Computer and Telecommunications Systems,pages 51?58, Oct. 2004.
22. C. A. Nicopoulos, D. Park, J. Kim, V. Narayanan, M. S. Yousif, and C. Das. ViChaR: A dynamic virtual channel regulator for network-on-chip routers. In Proc. Int. Symp. Microarchitecture, Dec. 2006.
23. V. S. Pai, P. Ranganathan, and S. V. Adve. RSIM: an executiondriven simulator for ILP-based shared-memory multiprocessors and uniprocessors. In Proc. Third Wkshp. on Computer Architecture Education, 1997.
24. M. Palesi, D. Patti, and F. Fazzino. NOXIM. http://noxim.sourceforge.net.
25. L.-S. Peh and W. J. Dally. A delay model and speculative architecture for pipelined routers. In Proc. Int. Symp. High Performance Computer Architecture, pages 255-266, Jan. 2001.
26. V. Puente, J. A. Gregorio, and R. Beivide. SICOSYS: an integrated framework for studying interconnection network performance in multiprocessor systems. In Proc. Euromicro Wkshp. Parallel, Distributed and Network-based Processing, pages 15-22, 2002.
27. J. Renau, B. Fraguela, W. L. J. Tuck, M. Prvulovic, L. Ceze, S. Sarangi, K. S. P. Sack, and P. Montesinos. SESC simulator. http://sesc.sourceforge.net, 2005.
28. SPLASH. http://www-flash.stanford.edu/apps/SPLASH/.
29. Sun. http://www.sun.com/processors/throughput/.
30. H.-S. Wang, X.-P. Zhu, L.-S. Peh, and S. Malik. Orion: A power-performance simulator for interconnection networks. In Proc. Int. Symp. Microarchitecture, pages 294-305, Nov. 2002.
31. M. Zhang and K. Asanovic. Victim replication: Maximizing capacity while hiding wire delay in tiled chip multiprocessors. In Proc. Int. Symp. Computer Architecture, pages 336-345, May 2005.