A high abstraction, high accuracy power estimation model for networks-on-chip

Proceedings of the 22nd Symposium on Integrated Circuits and Systems Design, SBCCI 2009

Volumn , Issue , 2009, Pages

  Ost, Luciano ^a   Guindani, Guilherme ^a   Indrusiak, Leandro Soares ^b   Reinbrecht, Cezar ^a   Raupp, Thiago ^a   Moraes, Fernando ^a  

^a PONTIFICAL CATHOLIC UNIVERSITY OF RIO GRANDE DO SUL   (Brazil)

^b UNIVERSITY OF YORK   (United Kingdom)

Author keywords

High abstraction modeling; Networks on chip; Power modeling

Indexed keywords

ABSTRACT MODELING; ABSTRACT MODELS; ABSTRACTION LEVEL; ABSTRACTION MODEL; ACCURACY LOSS; ACCURATE ESTIMATION; ACCURATE PERFORMANCE; ANALYTICAL DESCRIPTION; ART RESEARCH; BURST TRANSMISSION; COMMUNICATION BEHAVIOR; DESIGN DECISIONS; DESIGN FLOWS; DESIGN METRICS; DESIGN SPACE EXPLORATION; DESIGN SPACES; ENERGY CONSUMPTION; GRAPHIC TOOL; INDUSTRIAL TOOLS; MODELING NETWORKS; NETWORKS ON CHIPS; POWER DISSIPATION; POWER ESTIMATIONS; POWER PARAMETERS; PROOF OF CONCEPT; PTOLEMY II; RUNTIMES; SPEED-UPS; SYSTEM OBSERVABILITY; SYSTEMC;

DESIGN; ELECTRIC NETWORK TOPOLOGY; ELECTRIC POWER UTILIZATION; EMBEDDED SYSTEMS; ESTIMATION; INTEGRATED CIRCUITS; SPACE RESEARCH; WIRELESS NETWORKS;

ABSTRACTING;

EID: 70949100994     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1601896.1601936     Document Type: Conference Paper

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