Multisynchronous and fully asynchronous NoCs for GALS architectures

IEEE Design and Test of Computers

Volumn 25, Issue 6, 2008, Pages 572-580

  Sheibanyrad, Abbas ^a   Greiner, Alain ^b   Miro Panades, Ivan ^c  

^a TIMA LABORATORY   (France)

^b SORBONNE UNIVERSITÉ   (France)

^c DIF   (France)

Author keywords

Computer architecture; Integrated circuit interconnections; Power demand; Routing protocols; Synchronization; Throughput; Wires

Indexed keywords

BIOLOGICAL MATERIALS; COMPUTER NETWORKS; COMPUTERS; ELECTRIC CLOCKS; ELECTRIC NETWORK TOPOLOGY; INTEGRATED CIRCUITS; NETWORK ARCHITECTURE; ROUTING PROTOCOLS; WIRE;

CHIP AREAS; COMMUNICATION INFRASTRUCTURES; GALS ARCHITECTURES; INTEGRATED CIRCUIT INTERCONNECTIONS; MULTI-PROCESSORS; NETWORKS ON CHIPS; NEW DESIGNS; POWER DEMAND; SYNCHRONOUS CLOCKS;

COMPUTER ARCHITECTURE;

EID: 57949092860     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/MDT.2008.167     Document Type: Article

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