-
1
-
-
32044443861
-
Simulation of computer architectures: Simulators, benchmarks, methodologies, and recommendations
-
J. Yi and D. Lilja, "Simulation of computer architectures: simulators, benchmarks, methodologies, and recommendations," IEEE Transactions on Computers, vol. 55, no. 3, pp. 268-280, 2006.
-
(2006)
IEEE Transactions on Computers
, vol.55
, Issue.3
, pp. 268-280
-
-
Yi, J.1
Lilja, D.2
-
2
-
-
84926470638
-
-
Gem5's memory system
-
"Gem5's memory system," http://www.m5sim.org, 2013.
-
(2013)
-
-
-
3
-
-
84869225048
-
Accuracy evaluation of gem5 simulator system
-
A. Butko, R. Garibotti, L. Ost, and G. Sassatelli, "Accuracy evaluation of gem5 simulator system," in 7th Int'l Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2012, pp. 1-7.
-
(2012)
7th Int'l Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)
, pp. 1-7
-
-
Butko, A.1
Garibotti, R.2
Ost, L.3
Sassatelli, G.4
-
6
-
-
84881154274
-
Zsim: Fast and accurate microarchitectural simulation of thousand-core systems
-
New York, NY, USA: ACM
-
D. Sanchez and C. Kozyrakis, "Zsim: fast and accurate microarchitectural simulation of thousand-core systems," in Proceedings of the 40th Annual International Symposium on Computer Architecture, ser. ISCA '13. New York, NY, USA: ACM, 2013, pp. 475-486. [Online]. Available: http://doi.acm.org/10.1145/2485922.2485963
-
(2013)
Proceedings of the 40th Annual International Symposium on Computer Architecture, Ser. ISCA '13
, pp. 475-486
-
-
Sanchez, D.1
Kozyrakis, C.2
-
7
-
-
84871598067
-
Combining instruction set simulation and wcet analysis for embedded software performance estimation
-
S. Stattelmann, S. Ottlik, A. Viehl, O. Bringmann, and W. Rosenstiel, "Combining instruction set simulation and wcet analysis for embedded software performance estimation," in Industrial Embedded Systems (SIES), 2012 7th IEEE International Symposium on, 2012, pp. 295-298.
-
(2012)
Industrial Embedded Systems (SIES), 2012 7th IEEE International Symposium on
, pp. 295-298
-
-
Stattelmann, S.1
Ottlik, S.2
Viehl, A.3
Bringmann, O.4
Rosenstiel, W.5
-
8
-
-
77952555923
-
Slacksim: A platform for parallel simulations of cmps on cmps
-
Jul
-
J. Chen, M. Annavaram, and M. Dubois, "Slacksim: a platform for parallel simulations of cmps on cmps," SIGARCH Comput. Archit. News, vol. 37, no. 2, pp. 20-29, Jul. 2009. [Online]. Available: http://doi.acm.org/10.1145/1577129.1577134
-
(2009)
SIGARCH Comput. Archit. News
, vol.37
, Issue.2
, pp. 20-29
-
-
Chen, J.1
Annavaram, M.2
Dubois, M.3
-
9
-
-
77952563226
-
Graphite: A distributed parallel simulator for multicores
-
J. Miller, H. Kasture, G. Kurian, C. Gruenwald, N. Beckmann, C. Celio, J. Eastep, and A. Agarwal, "Graphite: A distributed parallel simulator for multicores," in High Performance Computer Architecture (HPCA), 2010 IEEE 16th International Symposium on, 2010, pp. 1-12.
-
(2010)
High Performance Computer Architecture (HPCA), 2010 IEEE 16th International Symposium on
, pp. 1-12
-
-
Miller, J.1
Kasture, H.2
Kurian, G.3
Gruenwald, C.4
Beckmann, N.5
Celio, C.6
Eastep, J.7
Agarwal, A.8
-
10
-
-
79956279112
-
Automatic tlm generation for early validation of multicore systems
-
S. Abdi, G. Schirner, Y. Hwang, D. Gajski, and L. Yu, "Automatic tlm generation for early validation of multicore systems," Design Test of Computers, IEEE, vol. 28, no. 3, pp. 10-19, 2011.
-
(2011)
Design Test of Computers, IEEE
, vol.28
, Issue.3
, pp. 10-19
-
-
Abdi, S.1
Schirner, G.2
Hwang, Y.3
Gajski, D.4
Yu, L.5
-
11
-
-
79957528059
-
Trace-driven simulation of multithreaded applications
-
A. Rico, A. Duran, F. Cabarcas, Y. Etsion, A. Ramirez, and M. Valero, "Trace-driven simulation of multithreaded applications," in Performance Analysis of Systems and Software (ISPASS), 2011 IEEE International Symposium on, 2011, pp. 87-96.
-
(2011)
Performance Analysis of Systems and Software (ISPASS), 2011 IEEE International Symposium on
, pp. 87-96
-
-
Rico, A.1
Duran, A.2
Cabarcas, F.3
Etsion, Y.4
Ramirez, A.5
Valero, M.6
-
12
-
-
55849111933
-
Tpts: A novel framework for very fast manycore processor architecture simulation
-
S. Cho, S. Demetriades, S. Evans, L. Jin, H. Lee, K. Lee, and M. Moeng, "Tpts: A novel framework for very fast manycore processor architecture simulation," in Int'l Conf. on Parallel Processing (ICPP), 2008, pp. 446-453.
-
(2008)
Int'l Conf. on Parallel Processing (ICPP)
, pp. 446-453
-
-
Cho, S.1
Demetriades, S.2
Evans, S.3
Jin, L.4
Lee, H.5
Lee, K.6
Moeng, M.7
-
13
-
-
0036469676
-
Simics: A full system simulation platform
-
P. Magnusson, M. Christensson, J. Eskilson, D. Forsgren, G. Hallberg, J. Hogberg, F. Larsson, A. Moestedt, and B. Werner, "Simics: A full system simulation platform," Computer, vol. 35, no. 2, pp. 50-58, 2002.
-
(2002)
Computer
, vol.35
, Issue.2
, pp. 50-58
-
-
Magnusson, P.1
Christensson, M.2
Eskilson, J.3
Forsgren, D.4
Hallberg, G.5
Hogberg, J.6
Larsson, F.7
Moestedt, A.8
Werner, B.9
-
15
-
-
79951589969
-
Netrace: Dependency-driven trace-based network-on-chip simulation
-
New York, NY, USA: ACM
-
J. Hestness, B. Grot, and S. W. Keckler, "Netrace: Dependency-driven trace-based network-on-chip simulation," in Proceedings of the Third International Workshop on Network on Chip Architectures, ser. NoCArc '10. New York, NY, USA: ACM, 2010, pp. 31-36. [Online]. Available: http://doi.acm.org/10.1145/1921249.1921258
-
(2010)
Proceedings of the Third International Workshop on Network on Chip Architectures, Ser. NoCArc '10
, pp. 31-36
-
-
Hestness, J.1
Grot, B.2
Keckler, S.W.3
-
17
-
-
0029179077
-
The splash-2 programs: Characterization and methodological considerations
-
S. Woo, M. Ohara, E. Torrie, J. Singh, and A. Gupta, "The splash-2 programs: characterization and methodological considerations," in Com-puter Architecture, 1995. Proceedings., 22nd Annual International Sym-posium on, 1995, pp. 24-36.
-
(1995)
Com-puter Architecture, 1995. Proceedings., 22nd Annual International Sym-posium on
, pp. 24-36
-
-
Woo, S.1
Ohara, M.2
Torrie, E.3
Singh, J.4
Gupta, A.5
|