Order is power: Selective packet interleaving for energy efficient networks-on-chip

Proceedings of the 2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC 2010

Volumn , Issue , 2010, Pages 37-42

  Berman, Amit ^a   Ginosar, Ran ^a   Keidar, Idit ^a  

^a TECHNION ISRAEL INSTITUTE OF TECHNOLOGY   (Israel)

Author keywords

Low power design techniques; Network on chip; Routing; VLSI interconnects

Indexed keywords

ANALYSIS AND SIMULATION; ENERGY EFFICIENT; LOW-POWER DESIGN; NETWORK ON CHIP; NETWORKS ON CHIPS; POWER CONSUMED; POWER CONSUMPTION; ROUTING; TRANSMISSION SCHEMES; VIRTUAL CHANNELS; VLSI INTERCONNECTS;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; INTERCONNECTION NETWORKS; MICROPROCESSOR CHIPS; PROGRAMMABLE LOGIC CONTROLLERS; SERVERS; TRANSMISSIONS; VLSI CIRCUITS;

ROUTERS;

EID: 78650951800     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSISOC.2010.5642624     Document Type: Conference Paper

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