HERMES: An infrastructure for low area overhead packet-switching networks on chip

Integration, the VLSI Journal

Volumn 38, Issue 1, 2004, Pages 69-93

  Moraes, Fernando ^a   Calazans, Ney ^a   Mello, Aline ^a   Möller, Leandro ^a   Ost, Luciano ^a  

^a PONTIFICAL CATHOLIC UNIVERSITY OF RIO GRANDE DO SUL   (Brazil)

Author keywords

Core based design; Network on chip; On chip interconnection; Switches; System on a chip

Indexed keywords

ALGORITHMS; INTEGRATED CIRCUITS; MICROPROCESSOR CHIPS; OPTICAL INTERCONNECTS; SEMICONDUCTOR DEVICE MANUFACTURE; SWITCHING NETWORKS; TOPOLOGY; TRANSISTORS;

CORE BASED DESIGN; NETWORK ON CHIP; ON-CHIP INTERCONNECTION; SYSTEM ON A CHIP;

PACKET SWITCHING;

EID: 9544237156     PISSN: 01679260     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.vlsi.2004.03.003     Document Type: Article

References (46)

1. International Sematech. International Technology Roadmap for Semiconductors - 2002 Update, 2002. Available at http://public.itrs.net.
2. R. Gupta, Y. Zorian, Introducing core-based system design, IEEE Des. Test Comput. 14 (4) (1997) 15-25.
3. R. Bergamaschi, et al., Automating the design of SOCs using cores, IEEE Des. Test Comput. 18 (5) (2001) 32-45.
4. G. Martin, H. Chang, System on chip design, in: The Nineth International Symposium on Integrated Circuits, Devices and Systems (ISIC'01), Tutorial 2, 2001.
5. S. Kumar, et al., A network on chip architecture and design methodology, in: IEEE Computer Society Annual Symposium on VLSI (ISVLSI'02), April 2002, pp. 105-112.
6. M. Millberg, E. Nilsson, R. Thid, S. Kumar, A. Jantsch, The Nostrum backbone - a communication protocol stack for networks on chip, in: Proceedings of the VLSI Design Conference, January 2004.
7. L. Benini, G. De Micheli, Powering networks on chips: energy-efficient and reliable interconnect design for SoCs, in: 14th International Symposium on Systems Synthesis (ISSS'01), October 2001, pp. 33-38.
8. L. Benini, G. De Micheli, Networks on chips: a new SoC paradigm, IEEE Comput. 35 (1) (2002) 70-78.
9. P. Guerrier, A. Greiner, Ageneric architecture for on-chip packet-switched interconections, in: Design Automation and Test in Europe (DATE'00), March 2000, pp. 250-256.
10. E. Rijpkema, K. Goossens, A. Rǎdulescu, Trade offs in the design of a router with both guaranteed and best-effort services for networks on chip, in: Design, Automation and Test in Europe (DATE'03), March 2003, pp. 350-355.
11. E. Rijpkema, K. Goossens, P. Wielage, Arouter architecture for networks on silicon, in: 2nd Workshop on Embedded Systems (PROGRESS'2001), November 2001, pp. 181-188.
12. J. Duato, S. Yalamanchili, L. Ni, Interconnection Networks: An Engineering Approach, Morgan Kaufmann, Los Altos, CA, 2002, 624p, revised edition.
13. J. Hennessy, D. Patterson, Computer Architecture: A Quantitative Approach, Morgan Kaufmann, San Francisco, CA, 1996, 760p.
14. K. Hwang, Advanced Computer Architecture: Parallelism, Scalability, Programmability, McGraw-Hill, New York, 1992, 672p.
15. L. Ni, et al., A survey of wormhole routing techniques in direct networks, IEEE Comput. 26 (2) (1993) 62-76.
16. T. Ye, L. Benini, G. De Micheli, Packetized on-chip interconnection communication analysis for MPSoC, in: Design Automation and Test in Europe (DATE'03), March 2003, pp. 344-349.
17. A. Andriahantenaina, A. Greiner, Micro-network for SoC: implementation of a 32-port SPIN network, in: Design Automation and Test in Europe Conference and Exhibition (DATE'03), March 2003, pp. 1128-1129.
18. A. Andriahantenaina, H. Charlery, A. Greiner, L. Mortiez, C. Zeferino, SPIN: a scalable, packet switched, on-chip micro-network, in: Design Automation and Test in Europe Conference and Exhibition (DATE'03), March 2003, pp. 70-73.
19. J. Liang, S. Swaminathan, R. Tessier, aSOC: A scalable, single-chip communications architecture, in: IEEE International Conference on Parallel Architectures and Compilation Techniques, October 2000, pp. 37-46.
20. W. Dally, B. Towles, Route packets, not wires: on-chip interconnection networks, in: 38th Design Automation Conference (DAC'01), June 2001, pp. 684-689.
21. M. Sgroi, M. Sheets, A. Mihal, K. Keutzer, S. Malik, J. Rabaey, A. Sangiovanni-Vincentelli, Addressing the system-on-chip interconnect woes through communication-based design, in: 38th Design Automation Conference (DAC'01), June 2001, pp. 667-672.
22. F. Karim, A. Nguyen, S. Dey, An interconnect architecture for network systems on chips, IEEE Micro 22 (5) (2002) 36-15.
23. F. Karim, A. Nguyen, S. Dey, R. Rao, On-chip communication architecture for OC-768 network processors, in: 38th Design Automation Conference (DAC'01), June 2001, pp. 678-683.
24. T. Marescaux, A. Bartic, D. Verkest, S. Vernalde, R. Lauwereins, Interconnection networks enable fine-grain dynamic multi-tasking on FPGAs, in: Field-Programmable Logic and Applications (FPL'02), September 2002, pp. 795-805.
25. T. Marescaux, J.-Y. Mignolet, A. Bartic, W. Moffat, D. Verkest, S. Vernalde, R. Lauwereins, Networks on chip as hardware components of an OS for reconfigurable systems, in: Field-Programmable Logic and Applications (FPL'03), September 2003.
26. A. Bartic, J.-Y. Mignolet, V. Nollet, T. Marescaux, J.-Y. Mignolet, D. Verkest, S. Vernalde, R. Lauwereins, Highly scalable network on chip for reconfigurable systems, in: International Symposium on System-on-Chip (SOC'2003), November 2003.
27. M. Forsell, A scalable high-performance computing solution for networks on chips, IEEE Micro 22 (5) (2002) 46-55.
28. D. Sigüenza-Tortosa, J. Nurmi, Proteo: a new approach to network-on-chip, in: IASTED International Conference on Communication Systems and Networks (CSN'02), September 2002.
29. I. Saastamoinen, M. Alho, J. Pirttimäki, J. Nurmi, Proteo interconnect IPs for networks-on-chip, in: IP Based SoC Design, October 2002.
30. I. Saastamoinen, M. Alho, J. Nurmi, Buffer implementation for proteo networks-on-chip, in: International Symposium on Circuits and Systems (ISCAS'03), May 2003, pp. II-113-II-116.
31. C. Zeferino, A. Susin, SoCIN: a parametric and scalable network-on-chip, in: 16th Symposium on Integrated Circuits and Systems Design (SBCCI'03), September 2003, pp. 169-174.
32. D. Wiklund, D. Liu, SoCBUS: switched network on chip for hard real time systems, in: International Parallel and Distributed Processing Symposium (IPDPS), April 2003.
33. E. Bolotin, I. Cidon, R. Ginosar, A. Kolodny, QNoC: QoS architecture and design process for network on chip, The Journal of Systems Architecture, Special Issue on Networks on Chip 50 (2) (2004) 105-128.
34. P. Pande, C. Grecu, A. Ivanov, R. Saleh, Design of a switch for network on chip applications, in: International Symposium on Circuits and Systems (ISCAS'03), May 2003, pp. 217-220.
35. C. Grecu, P. Pande, A. Ivanov, R. Saleh, A scalable communication-centric SoC interconnect architecture, in: IEEE International Symposium on Quality Electronic Design (ISQED'2004), 2004.
36. M. Dall'Osso, G. Biccari, L. Giovannini, D. Bertozzi, L. Benini, Xpipes: a latency insensitive parameterized network-on-chip architecture for multi-processor SoCs, in: International Conference on Computer Design (ICCD'03), 2003, pp. 536-539.
37. F. Moraes, A. Mello, L. Möller, L. Ost, N. Calazans, A low area overhead packet-switched network on chip: architecture and prototyping, in: IFIP Very Large Scale Integration (VLSI-SOC), 2003, pp. 318-323.
38. C. Glass, L. Ni, The turn model for adaptive routing, J. Assoc. Comput. Mach. 41 (5) (1994) 874-902.
39. J. Day, H. Zimmermman, The OSI reference model, Proc. IEEE 71 (12) (1983) 1334-1340.
40. A. Hemani, T. Meincke, S. Kumar, A. Postula, T. Olsson P. Nilsson, J. Öberg, P. Ellervee, D. Lundqvist, Lowering power consumption in clock by using globally asynchronous, locally synchronous design style, in: 36th Design Automation Conference (DAC'99), 1999, pp. 873-878.
41. P. Mohapatra, Wormhole routing techniques for directly connected multicomputer systems, ACM Comput. Surv. 30 (3) (1998) 374-410.
42. Model Technology. ModelSim Foreign Language Interface, Version 5.5e, 2001.
43. Xilinx Inc. Virtex-II Platform FPGA User Guide. July 2002, available at: http://www.xilinx.com.
44. N. Calazans, E. Moreno, F. Hessel, V. Rosa, F. Moraes, E. Carara, From VHDL register transfer level to systemC transaction level modeling: a comparative case study, in: 16th Symposium on Integrated Circuits and Systems Design, (SBCCI'03), 2003, pp. 355-360.
45. N. Calazans, F. Moraes, Integrating the teaching of computer organization and architecture with digital hardware design early in undergraduate courses, IEEE Trans. Educat. 44 (2) (2001) 109-119.
46. A. Mello, Möller, L. SoC multiprocessing architectures: a study of different interconnection topologies. End of Term Work, FACIN-PUCRS, July 2003, 120p. (in Portuguese), available at http://www.inf.pucrs.br/~moraes/papers/ tc_multiproc.pdf.