-
1
-
-
16244409520
-
Multi-objective mapping for mesh-based NoC architectures
-
G. Ascia, V. Catania, and M. Palesi. Multi-objective mapping for mesh-based NoC architectures. In CODES+ISSS, 2004.
-
(2004)
CODES+ISSS
-
-
Ascia, G.1
Catania, V.2
Palesi, M.3
-
2
-
-
0000703331
-
Applying new scheduling theory to static priority pre-emptive scheduling
-
N. Audsley, A. Burns, M. Richardson, K. Tindell, and A. Wellings. Applying new scheduling theory to static priority pre-emptive scheduling. Software Engineering Journal, 8(5):284-292, 1993.
-
(1993)
Software Engineering Journal
, vol.8
, Issue.5
, pp. 284-292
-
-
Audsley, N.1
Burns, A.2
Richardson, M.3
Tindell, K.4
Wellings, A.5
-
3
-
-
0036530772
-
A fast and elitist multiobjective genetic algorithm: NSGA-II
-
DOI 10.1109/4235.996017, PII S1089778X02041012
-
K. Deb, A. Pratap, S. Agarwal, and T. Meyarivan. A Fast and Elitist Multiobjective Genetic Algorithm: NSGA-II. IEEE Transactions on Evolutionary Computation, 6(2):182-197, April 2002. (Pubitemid 34555372)
-
(2002)
IEEE Transactions on Evolutionary Computation
, vol.6
, Issue.2
, pp. 182-197
-
-
Deb, K.1
Pratap, A.2
Agarwal, S.3
Meyarivan, T.4
-
5
-
-
67649207711
-
Low-power coding for networks-on-chip with virtual channels
-
A. Garcia-Ortiz, L. Indrusiak, T. Murgan, and M. Glesner. Low-power coding for networks-on-chip with virtual channels. Journal of Low Power Electronics, 5(1):77-84, 2009.
-
(2009)
Journal of Low Power Electronics
, vol.5
, Issue.1
, pp. 77-84
-
-
Garcia-Ortiz, A.1
Indrusiak, L.2
Murgan, T.3
Glesner, M.4
-
6
-
-
34548137799
-
A multi-objective evolutionary algorithm based optimization model for network-on-chip synthesis
-
R. K. Jena and G. K. Sharma. A multi-objective evolutionary algorithm based optimization model for network-on-chip synthesis. In ITNG, 2007.
-
(2007)
ITNG
-
-
Jena, R.K.1
Sharma, G.K.2
-
7
-
-
80052581008
-
Genetic mapping of hard real-time applications onto NoC-based MPSoCs: A first approach
-
P. Mesidis and L. Indrusiak. Genetic mapping of hard real-time applications onto NoC-based MPSoCs: A first approach. In ReCoSoC, 2011.
-
(2011)
ReCoSoC
-
-
Mesidis, P.1
Indrusiak, L.2
-
8
-
-
37849039546
-
On the necessity of combining coding with spacing and shielding for improving performance and power in very deep sub-micron interconnects
-
PATMOS, Springer
-
T. Murgan, P. B. Bacinschi, S. Pandey, A. G. Ortiz, and M. Glesner. On the necessity of combining coding with spacing and shielding for improving performance and power in very deep sub-micron interconnects. In PATMOS, volume 4644 of Lecture Notes in Computer Science. Springer, 2007.
-
(2007)
Lecture Notes in Computer Science
, vol.4644
-
-
Murgan, T.1
Bacinschi, P.B.2
Pandey, S.3
Ortiz, A.G.4
Glesner, M.5
-
9
-
-
78650284598
-
Customized computer-aided application mapping on NoC infrastructure using multi-objective optimization
-
N. Nedjah, M. Silva, and L. Mourelle. Customized computer-aided application mapping on NoC infrastructure using multi-objective optimization. JSA, 57(1):79 - 94, 2011.
-
(2011)
JSA
, vol.57
, Issue.1
, pp. 79-94
-
-
Nedjah, N.1
Silva, M.2
Mourelle, L.3
-
10
-
-
70450247054
-
Respir: A response surface-based pareto iterative refinement for application-specific design space exploration
-
G. Palermo, C. Silvano, and V. Zaccaria. Respir: A response surface-based pareto iterative refinement for application-specific design space exploration. IEEE TCAD, 28(12):1816-1829, 2009.
-
(2009)
IEEE TCAD
, vol.28
, Issue.12
, pp. 1816-1829
-
-
Palermo, G.1
Silvano, C.2
Zaccaria, V.3
-
11
-
-
79955415149
-
Data encoding schemes in networks on chip
-
M. Palesi, G. Ascia, F. Fazzino, and V. Catania. Data encoding schemes in networks on chip. IEEE TCAD, 30(5):774 -786, 2011.
-
(2011)
IEEE TCAD
, vol.30
, Issue.5
, pp. 774-786
-
-
Palesi, M.1
Ascia, G.2
Fazzino, F.3
Catania, V.4
-
13
-
-
84881115715
-
Swift: A low-power network-on-chip implementing the token flow control router architecture with swing-reduced interconnects
-
J. Postman, T. Krishna, C. Edmonds, L.-S. Peh, and P. Chiang. Swift: A low-power network-on-chip implementing the token flow control router architecture with swing-reduced interconnects. IEEE TVLSI, 21(8):1432-1446, 2013.
-
(2013)
IEEE TVLSI
, vol.21
, Issue.8
, pp. 1432-1446
-
-
Postman, J.1
Krishna, T.2
Edmonds, C.3
Peh, L.-S.4
Chiang, P.5
-
14
-
-
84869217970
-
Using genetic algorithms to map hard real-time on NoC-based systems
-
A. Racu and L. Indrusiak. Using genetic algorithms to map hard real-time on NoC-based systems. In ReCoSoC, 2012.
-
(2012)
ReCoSoC
-
-
Racu, A.1
Indrusiak, L.2
-
16
-
-
36949017447
-
A robust edge encoding technique for energy-efficient multi-cycle interconnect
-
IEEE
-
J. Seo, D. Sylvester, D. Blaauw, H. Kaul, and R. Krishnamurthy. A robust edge encoding technique for energy-efficient multi-cycle interconnect. In ISLPED. IEEE, 2007.
-
(2007)
ISLPED
-
-
Seo, J.1
Sylvester, D.2
Blaauw, D.3
Kaul, H.4
Krishnamurthy, R.5
-
17
-
-
79957564087
-
Schedulability analysis for real time on-chip communication with wormhole switching
-
Z. Shi, A. Burns, and L. Indrusiak. Schedulability analysis for real time on-chip communication with wormhole switching. IJERTCS, 1(2):1-22, 2010.
-
(2010)
IJERTCS
, vol.1
, Issue.2
, pp. 1-22
-
-
Shi, Z.1
Burns, A.2
Indrusiak, L.3
-
18
-
-
50249127218
-
Pareto based multi-objective mapping ip cores onto NoC architectures
-
W. Zhou, Y. Zhang, and Z. Mao. Pareto based multi-objective mapping ip cores onto NoC architectures. In APCCAS, 2006.
-
(2006)
APCCAS
-
-
Zhou, W.1
Zhang, Y.2
Mao, Z.3
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