Optimizing the NoC slack through voltage and frequency scaling in hard real-time embedded systems

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 33, Issue 11, 2014, Pages 1632-1643

  Zhan, Jia ^a   Stoimenov, Nikolay ^c   Ouyang, Jin ^d   Thiele, Lothar ^c   Narayanan, Vijaykrishnan ^a   Xie, Yuan ^b  

^a PENNSYLVANIA STATE UNIVERSITY   (United States)

^b University of California   (United States)

^c ETH ZURICH   (Switzerland)

^d NVIDIA   (United States)

Author keywords

Dynamic voltage and frequency scaling (DVFS); network calculus; network on chip (NoC); slack; worst case delay analysis

Indexed keywords

DYNAMIC VOLTAGE AND FREQUENCY SCALING; NETWORK CALCULUS; NETWORK-ON-CHIP(NOC); SLACK; WORST-CASE DELAY ANALYSIS;

EID: 84908265342     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2014.2347921     Document Type: Article

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