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Volumn 2015-April, Issue , 2015, Pages 537-542

Worst-case communication time analysis of networks-on-chip with shared virtual channels

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; INTERACTIVE COMPUTER SYSTEMS; NETWORK-ON-CHIP;

EID: 84945958987     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.7873/date.2015.0023     Document Type: Conference Paper
Times cited : (37)

References (23)
  • 1
    • 80455129094 scopus 로고    scopus 로고
    • Real-time communication analysis for networks with two-stage arbitration
    • October
    • J. Diemer, J. Rox, M. Negrean, S. Stein, and R. Ernst, Real-Time Communication Analysis for Networks with Two-Stage Arbitration, in EMSOFT'11, October 2011
    • (2011) EMSOFT'11
    • Diemer, J.1    Rox, J.2    Negrean, M.3    Stein, S.4    Ernst, R.5
  • 6
    • 0034785285 scopus 로고    scopus 로고
    • Powering networks on chips: Energyefficient and reliable interconnect design for SoCs
    • ser. ISSS '01. New York, NY, USA: ACM
    • L. Benini and G. De Micheli, Powering networks on chips: Energyefficient and reliable interconnect design for SoCs, in Proceedings of the 14th International Symposium on Systems Synthesis, ser. ISSS '01. New York, NY, USA: ACM, 2001, pp. 33-38
    • (2001) Proceedings of the 14th International Symposium on Systems Synthesis , pp. 33-38
    • Benini, L.1    De Micheli, G.2
  • 7
    • 27344456043 scopus 로고    scopus 로고
    • Athereal network on chip: Concepts, architectures, and implementations
    • K. Goossens, J. Dielissen, and A. Rədulescu, Athereal Network on Chip: Concepts, Architectures, and Implementations, IEEE DESIGN &TEST, vol. 22, no. 5, pp. 414-421, 2005
    • (2005) IEEE DESIGN &TEST , vol.22 , Issue.5 , pp. 414-421
    • Goossens, K.1    Dielissen, J.2    Rədulescu, A.3
  • 9
    • 1242309790 scopus 로고    scopus 로고
    • QNoC: Qos architecture and design process for network on chip
    • E. Bolotin, I. Cidon, R. Ginosar, and A. Kolodny, QNoC: QoS Architecture and Design Process for Network on Chip, J. Syst. Archit., vol. 50, no. 2-3, pp. 105-128, 2004
    • (2004) J. Syst. Archit , vol.50 , Issue.2-3 , pp. 105-128
    • Bolotin, E.1    Cidon, I.2    Ginosar, R.3    Kolodny, A.4
  • 10
    • 52649094492 scopus 로고    scopus 로고
    • Globally-synchronized frames for guaranteed quality-of-service in on-chip networks
    • J. Lee, M. C. Ng, and K. Asanovic, Globally-Synchronized Frames for Guaranteed Quality-of-Service in On-Chip Networks, in ISCA, 2008
    • (2008) ISCA
    • Lee, J.1    Ng, M.C.2    Asanovic, K.3
  • 11
    • 44149099590 scopus 로고    scopus 로고
    • Real-time communication analysis for on-chip networks with wormhole switching
    • Washington, DC, USA: IEEE Computer Society
    • Z. Shi and A. Burns, Real-time communication analysis for on-chip networks with wormhole switching, in Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip. Washington, DC, USA: IEEE Computer Society, 2008, pp. 161-170
    • (2008) Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip , pp. 161-170
    • Shi, Z.1    Burns, A.2
  • 15
    • 0032655137 scopus 로고    scopus 로고
    • The iSLIP scheduling algorithm for input-queued switches
    • N. McKeown, The iSLIP scheduling algorithm for input-queued switches, IEEE/ACM Transactions on Networking (TON), vol. 7, no. 2, pp. 188-201, 1999
    • (1999) IEEE/ACM Transactions on Networking (TON) , vol.7 , Issue.2 , pp. 188-201
    • McKeown, N.1
  • 19
    • 84910130172 scopus 로고    scopus 로고
    • Compositional performance analysis in python with PyCPA
    • J. Diemer, P. Axer, and R. Ernst, Compositional performance analysis in python with PyCPA, Proc. of WATERS, 2012
    • (2012) Proc. of WATERS
    • Diemer, J.1    Axer, P.2    Ernst, R.3
  • 20
    • 0028396945 scopus 로고
    • An extendible approach for analyzing fixed priority hard real-time tasks
    • K. Tindell, A. Burns, and A. Wellings, An extendible approach for analyzing fixed priority hard real-time tasks, Real-Time Systems, vol. 6, no. 2, 1994
    • (1994) Real-Time Systems , vol.6 , Issue.2
    • Tindell, K.1    Burns, A.2    Wellings, A.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.