Providing multiple hard latency and throughput guarantees for packet switching networks on chip

Computers and Electrical Engineering

Volumn 39, Issue 8, 2013, Pages 2603-2622

  Heisswolf, Jan ^a   König, Ralf ^a   Kupper, Martin ^a   Becker, Jürgen ^a  

^a KARLSRUHE INSTITUTE OF TECHNOLOGY   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION REQUIREMENTS; BANDWIDTH REQUIREMENT; COMMUNICATION RESOURCES; COMMUNICATION SCHEMES; DISTRIBUTED APPLICATIONS; DISTRIBUTED RESERVATION; MANY-CORE ARCHITECTURE; THROUGHPUT GUARANTEES;

BANDWIDTH; COMMUNICATION; COMPUTER ARCHITECTURE; EMBEDDED SYSTEMS; ENERGY UTILIZATION; QUALITY OF SERVICE; ROUTERS; TELECOMMUNICATION NETWORKS; THROUGHPUT;

TELECOMMUNICATION SYSTEMS;

EID: 84888636940     PISSN: 00457906     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.compeleceng.2013.06.005     Document Type: Conference Paper

References (39)

1. L. Benini, and G. De Micheli Networks on chips: a new soc paradigm Computer 35 1 2002 70 78 10.1109/2.976921
2. Clermidy F, Bernard C, Lemaire R, Martin J, Miro-Panades I, Thonnart Y, et al. MAGALI: a network-on-chip based multi-core system-on-chip for MIMO 4G SDR. In: ICICDT, 2010, pp. 74-77. http://dx.doi.org/10.1109/ICICDT.2010.5510291.
3. Lattard D, B E, et al. A reconfigurable baseband platform based on an asynchronous network-on-chip. IEEE J Solid-State Circuit. http://dx.doi.org/10. 1109/JSSC.2007.909339.
4. Jalier C, Lattard D, Jerraya A, Sassatelli G, Benoit P, Torres L. Heterogeneous vs homogeneous mpsoc approaches for a mobile lte modem. In: Design, automation test in europe conference exhibition (DATE), 2010; 2010. p. 184-9. http://dx.doi.org/10.1109/DATE.2010.5457213.
5. S. Borkar, and A.A. Chien The future of microprocessors Commun ACM 54 5 2011 67 77 10.1145/1941487.1941507
6. N. Voros, A. Rosti, and M. Hübner Dynamic system reconfiguration in heterogeneous platforms: the MORPHEUS approach 2009 Springer
7. Bell S, Edwards B, Amann J, Conlin R, Joyce K, Leung V, et al. Tile64 - processor: A 64-core soc with mesh interconnect. In: Solid-state circuits conference, 2008. ISSCC 2008. Digest of technical papers. IEEE international; 2008. p. 88-598. http://dx.doi.org/10.1109/ISSCC.2008.4523070.
8. Howard J, Dighe S, Hoskote Y, Vangal S, Finan D, Ruhl G, et al. A 48-core ia-32 message-passing processor with dvfs in 45 nm cmos. In: Solid-state circuits conference digest of technical papers (ISSCC), 2010 IEEE international; 2010. p. 108-9. http://dx.doi.org/10.1109/ISSCC.2010.5434077.
9. S. Borkar Thousand core chips: a technology perspective Proceedings of the 44th annual design automation conference, DAC '07 2007 ACM New York (NY, USA) 746 749 http://dx.doi.org/10.1145/1278480.1278667
10. D. Bertozzi, A. Jalabert, S. Murali, R. Tamhankar, S. Stergiou, and L. Benini Noc synthesis flow for customized domain specific multiprocessor systems-on-chip IEEE Trans Parallel Distrib Syst 16 2 2005 113 129 10.1109/TPDS.2005.22
11. Heisswolf J, Konig R, Becker J. A scalable noc router design providing qos support using weighted round robin scheduling. In: 2012 IEEE 10th international symposium on parallel and distributed processing with applications (ISPA); 2012. p. 625-32. http://dx.doi.org/10.1109/ISPA.2012.93.
12. B. Grot, S.W. Keckler, and O. Mutlu Preemptive virtual clock: a flexible, efficient, and cost-effective qos scheme for networks-on-chip Proceedings of the 42nd annual IEEE/ACM international symposium on microarchitecture, MICRO 42 2009 ACM New York (NY, USA) 268 279 http://dx.doi.org/10.1145/1669112.1669149
13. Heisswolf J, Zaib A, Weichslgartner A, Konig R, Wild T, Teich J, et al. Hardware-assisted decentralized resource management for networks on chip with qos. In: 2012 IEEE 26th international parallel and distributed processing symposium workshops PhD forum (IPDPSW); 2012. p. 234-41. http://dx.doi.org/10. 1109/IPDPSW.2012.25.
14. Bjerregaard T, Sparso J. A router architecture for connection-oriented service guarantees in the mango clockless network-on-chip. In: Proceedings design, automation and test in europe, 2005, vol. 2; 2005. p. 1226-31. http://dx.doi.org/10.1109/DATE.2005.36.
15. Y.-C. Lan, H.-A. Lin, S.-H. Lo, Y.H. Hu, and S.-J. Chen A bidirectional noc (binoc) architecture with dynamic self-reconfigurable channel IEEE Trans Comput-Aid Des Integr Circ Syst 30 3 2011 427 440 10.1109/TCAD.2010.2086930
16. Millberg M, Nilsson E, Thid R, Jantsch A. Guaranteed bandwidth using looped containers in temporally disjoint networks within the nostrum network on chip. In: Proceedings, design, automation and test in europe conference and exhibition, 2004, vol. 2; 2004. p. 890-5. http://dx.doi.org/10.1109/DATE.2004. 1269001.
17. Lu Z, Jantsch A. TDM virtual-circuit configuration for network-on-chip, VLSI. http://dx.doi.org/10.1109/TVLSI.2008.2000673.
18. Goossens K, Dielissen J, Radulescu A. Æthereal network on chip: concepts, architectures, and implementations IEEE Des Test. http://dx.doi.org/ 10.1109/MDT.2005.99.
19. Marescaux T, Bricke B, Debacker P, Nollet V, Corporaal H. Dynamic time-slot allocation for qos enabled networks on chip. In: 3rd Workshop on embedded systems for real-time multimedia, 2005; 2005. p. 47-52. http://dx.doi.org/10.1109/ESTMED.2005.1518069.
20. Wang Y, Zhou K, Lu Z, Yang H. Dynamic tdm virtual circuit implementation for noc. In: IEEE Asia Pacific conference on circuits and systems, 2008. APCCAS 2008; 2008. p. 1533-6. http://dx.doi.org/10.1109/APCCAS.2008.4746325.
21. R. Stefan, and K. Goossens A tdm slot allocation flow based on multipath routing in nocs Microprocess Microsyst 35 2 2011 130 138 10.1016/j.micpro.2010. 09.007 [Special issue on network-on-chip architectures and design methodologies]
22. Kwon W-C, Yoo S, Um J, Jeong S-W. In-network reorder buffer to improve overall noc performance while resolving the in-order requirement problem. In: Design, automation test in europe conference exhibition, 2009. DATE '09; 2009. p. 1058-63. http://dx.doi.org/10.1109/DATE.2009.5090821.
23. S. Murali, D. Atienza, L. Benini, and G. De Michel A multi-path routing strategy with guaranteed in-order packet delivery and fault-tolerance for networks on chip Proceedings of the 43rd annual design automation conference, DAC '06 2006 ACM New York (NY, USA) 845 848 http://dx.doi.org/10.1145/1146909. 1147124
24. Bolotin E, Cidon I, Ginosar R, Kolodny A. QNoC: QoS architecture and design process for network on chip. J Syst Archi. http://dx.doi.org/10.1016/j. sysarc.2003.07.004.
25. J.W. Lee, M.C. Ng, and K. Asanovic Globally-synchronized frames for guaranteed quality-of-service in on-chip networks SIGARCH Comput Archit News 36 2008 89 100 10.1145/1394608.1382130
26. B. Grot, J. Hestness, S.W. Keckler, and O. Mutlu Kilo-noc: a heterogeneous network-on-chip architecture for scalability and service guarantees SIGARCH Comput Archit News 39 3 2011 401 412 10.1145/2024723.2000112
27. M. Katevenis, S. Sidiropoulos, and C. Courcoubetis Weighted round-robin cell multiplexing in a general-purpose atm switch chip IEEE J Selected Area Commun 9 8 1991 1265 1279 10.1109/49.105173
28. Wang J, Levy Y. Managing performance using weighted round-robin. In: Proceedings. ISCC 2000. Fifth IEEE symposium on computers and communications, 2000; 2000. p. 785-92. http://dx.doi.org/10.1109/ISCC.2000.860739.
29. Qian Y, Lu Z, Dou Q. Qos scheduling for nocs: strict priority queueing versus weighted round robin. In: 2010 IEEE international conference on computer design (ICCD); 2010. p. 52-59. http://dx.doi.org/10.1109/ICCD.2010.5647577.
30. J. Hu, and R. Marculescu Dyad: smart routing for networks-on-chip Proceedings of the 41st annual design automation conference, DAC '04 2004 ACM New York (NY, USA) 260 263 http://dx.doi.org/10.1145/996566.996638
31. F. Liu, H. Gu, and Y. Yang Dtbr: a dynamic thermal-balance routing algorithm for network-on-chip Comput Electr Eng 38 2 2012 270 281 10.1016/j.compeleceng.2011.12.006
32. Bourgade R, Rochange C, De Michiel M, Sainrat P. Mbba: a multi-bandwidth bus arbiter for hard real-time. In: 2010 5th International Conference on Embedded and multimedia computing (EMC); 2010. p. 1-7. http://dx.doi.org/10. 1109/EMC.2010.5575754.
33. Hu J, Marculescu R. Energy-aware mapping for tile-based noc architectures under performance constraints. In: Proceedings of the ASP-DAC 2003 design automation conference, 2003. Asia and South Pacific; 2003. p. 233-9. http://dx.doi.org/10.1109/ASPDAC.2003.1195022.
34. Wang X, Yang M, Jiang Y, Liu P. Power-aware mapping for network-on-chip architectures under bandwidth and latency constraints. In: EM-Com 2009. 4th international conference on embedded and multimedia computing, 2009; 2009. p. 1-6. http://dx.doi.org/10.1109/EM-COM.2009.5402985.
35. L. Zhang, E.E. Regentova, and X. Tan Packet switching optical network-on-chip architectures Comput Electr Eng 39 2 2013 697 714 10.1016/j.compeleceng.2012.03.006
36. L. Zhang, M. Yang, Y. Jiang, and E. Regentova Architectures and routing schemes for optical network-on-chips Comput Electr Eng 35 6 2009 856 877 10.1016/j.compeleceng.2008.09.010
37. T.C. Xu, A.W. Yin, P. Liljeberg, and H. Tenhunen A study of 3d network-on-chip design for data parallel h.264 coding Microprocess Microsyst 35 7 2011 603 612 10.1016/j.micpro.2011.06.009
38. Y. Chen, Z. Lu, L. Xie, J. Li, and M. Zhang A single-cycle output buffered router with layered switching for networks-on-chips Comput Electr Eng 38 4 2012 906 916 10.1016/j.compeleceng.2012.02.018
39. A. Radulescu, J. Dielissen, S. Pestana, O. Gangwal, E. Rijpkema, and P. Wielage An efficient on-chip ni offering guaranteed services, shared-memory abstraction, and flexible network configuration IEEE Trans Comput-Aid Des Integr Circ Syst 24 1 2005 4 17 10.1109/TCAD.2004.839493(410) 24