Real-time low-power task mapping in Networks-on-Chip

Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI

Volumn , Issue , 2013, Pages 14-19

  Sayuti, M Norazizi Sham Mohd ^a   Indrusiak, Leandro Soares ^a  

^a UNIVERSITY OF YORK   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

EMBEDDED SYSTEMS; GENETIC ALGORITHMS; LOW POWER ELECTRONICS; MAPPING; REAL TIME SYSTEMS;

% REDUCTIONS; COMMUNICATION PATH; IN NETWORKS; LOW POWER; NETWORKS ON CHIPS; PACKET ROUTING; POWER MINIMIZATION; REAL- TIME; STATE-OF-THE-ART APPROACH; TASKS MAPPING;

NETWORK-ON-CHIP;

EID: 84893594029     PISSN: 21593469     EISSN: 21593477     Source Type: Conference Proceeding    
DOI: 10.1109/ISVLSI.2013.6654616     Document Type: Conference Paper

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