An iterative computational technique for performance evaluation of Networks-on-Chip

IEEE Transactions on Computers

Volumn 62, Issue 8, 2013, Pages 1641-1655

  Foroutan, Sahar ^a   Thonnart, Yvain ^b   Pétrot, Frédéric ^a  

^a TIMA LABORATORY   (France)

^b CEA LETI   (France)

Author keywords

Multiprocessor systems on chip (MPSoCs); Networks on chip (NoCs); Performance analysis

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER SIMULATION; ITERATIVE METHODS; MICROPROCESSOR CHIPS; VLSI CIRCUITS;

ANALYTICAL PERFORMANCE EVALUATIONS; COMPUTATIONAL TECHNIQUE; CYCLE-ACCURATE SIMULATION; DESIGN SPACE EXPLORATION; IS PERFORMANCE EVALUATION; MULTIPROCESSOR SYSTEMS ON CHIPS; NETWORKS ON CHIPS; PERFORMANCE ANALYSIS;

ROUTERS;

EID: 84897727802     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2012.85     Document Type: Article

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