Fast simulation of networks-on-chip with priority-preemptive arbitration

ACM Transactions on Design Automation of Electronic Systems

Volumn 20, Issue 4, 2015, Pages

  Indrusiak, Leandro Soares ^a   Harbin, James ^a   Dos Santos, Osmar Marchi ^b  

^a UNIVERSITY OF YORK   (United Kingdom)

^b FEDERAL UNIVERSITY OF SANTA MARIA   (Brazil)

Author keywords

Network on chip; Transaction level simulation

Indexed keywords

COMPUTER ARCHITECTURE; INTEGRATED CIRCUIT DESIGN; NETWORK ARCHITECTURE; NETWORK-ON-CHIP; SERVERS;

COMMUNICATION LATENCY; DESIGN ITERATION; INTERCONNECT ARCHITECTURES; NETWORK-ON-CHIP ARCHITECTURES; NETWORKS ON CHIPS; ON-CHIP MULTIPROCESSOR; TIME-CONSUMING PARTS; TRANSACTION LEVEL;

INTEGRATED CIRCUIT INTERCONNECTS;

EID: 84942932254     PISSN: 10844309     EISSN: 15577309     Source Type: Journal    
DOI: 10.1145/2755559     Document Type: Article

References (36)

1. Anant Agarwal. 2007. The tile processor: A 64-core multicore for embedded processing. In Proceedings of the 11th Annual Workshop on High Performance Embedded Computing (HPEC).
2. John Aynsley. 2009. TLM-2.0 Language Reference Manual. Open SystemC Initiative (OSCI).
3. Marco Bekooij, Rob Hoes, Orlando Moreira, Peter Poplark, Milan Pastrnak, Bart Mesman, Jan David Mol, Sander Stuijk, Valentin Gheorghita, and Jef Van Meerbergen. 2005. Dataflow analysis for real-time embedded multiprocessor system design. In Dynamic and Robust Streaming in and between Connected Consumer-Electronic Devices. Philips Research, vol. 3, Springer, Berlin, 81-108.
4. T. Bjerregaard and J. Sparso. 2004. Virtual channel designs for guaranteeing bandwidth in asynchronous network-on-chip. In Proceedings of the NORCHIP Conference. 269-272.
5. Evgeny Bolotin, Israel Cidon, Ran Ginosar, and Avinoam Kolodny. 2004. QNoC: QoS architecture and design process for network on chip. J. Syst. Archit. 50, 2-3 (2004), 105-128.
6. Alan Burns and Andy Wellings. 2009. Real-Time Systems and Programming Languages: Ada, Real-Time Java and C/Real-Time POSIX 4th Ed. Harlow: Addison Wesley.
7. L. Cai and D. Gajski. 2003. Transaction level modeling: An overview. In Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis. IEEE, 19-24.
8. M. Eggenberger and M. Radetzki. 2013. Scalable parallel simulation of networks on chip. In Proceedings of the 7th IEEE/ACM International Symposium on Networks on Chip (NoCS). 1-8.
9. J. Eker, J. W. Janneck, E. A. Lee, J. Liu, X. Liu, J. Luding, S. Neuendorffer, S. Sachs, and Y. Xiong. 2003. Taming heterogeneity - the Ptolemy approach. Proc. IEEE 91, 1 (2003), 127-144.
10. N. Genko, D. Atienza, G. De Micheli, L. Benini, J. M. Mendias, R. Hermida, and F. Catthoor. 2005. A novel approach for network on chip emulation. In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS). 2365-2368.
11. K. Goossens, J. Dielissen, and A. Radulescu. 2005. AEthereal network on chip: Concepts, architectures, and implementations. IEEE Des. Test Comput. 22, 5 (2005), 414-421.
12. Kris Heid, Haoyuan Ying, Christian Hochberger, and Klaus Hofmann. 2014. LatEst: Latency estimation and high speed evaluation for wormhole switched networks-on-chip. In Proceedings of the 9th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC). IEEE.
13. Mohammad Hosseinabady and Jose L. Nunez-Yanez. 2010. SystemC architectural transaction level modelling for large NoCs. In Proceedings of the ECSI Forum on Specification and Design Languages (FDL).
14. Leandro Soares Indrusiak. 2014. End-to-end schedulability tests for multiprocessor embedded systems based on networks-on-chip with priority-preemptive arbitration. J. Syst. Archit. 60, 7 (2014), 553-561.
15. L. S. Indrusiak, L. C. Ost, F. G. Moraes, S. Maatta, J. Nurmi, L. Moller, and M. Glesner. 2010. Evaluating the impact of communication latency on applications running over on-chip multiprocessing platforms: a layered approach. In Proceedings of the 8th IEEE International Conference on Industrial Informatics (INDIN).
16. Leandro Soares Indrusiak and Osmar Marchi dos Santos. 2011. Fast and accurate transaction-level model of a wormhole network-on-chip with priority preemptive virtual channel arbitration. In Proceedings of the Design Automation and Test in Europe Conference (DATE). 1089-1094.
17. Nan Jiang, D.U. Becker, G. Michelogiamakis, J. Balfour, B. Towles, D. E. Shaw, J. Kim, and W. J. Dally. 2013. A detailed and flexible cycle-accurate network-on-chip simulator. In Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS). 86-96.
18. H. Kashif and H. Patel. 2014. Bounding buffer space requirements for real-time priority-aware networks. In Proceedings of the 19th Asia and South Pacific Design Automation Conference (ASP-DAC). 113-118.
19. Abbas Eslami Kiasari, Axel Jantsch, and Zhonghai Lu. 2013. Mathematical formalisms for performance evaluation of networks-on-chip. ACM Comput. Surv. 45, 3 (2013), 38:1-38:41.
20. A. Kohler and M. Radetzki. 2009. A systemc TLM2 model of communication in wormhole switched networkson-chip. In Proceedings of the Forum on Specification Design Languages (FDL). 1-4.
21. Kai-Li Lin, Chen-Kang Lo, and Ren-Song Tsay. 2010. Source-level timing annotation for fast and accurate TLM computation model generation. In Proceedings of the 15th Asia and South Pacific Design Automation Conference (ASP-DAC). 235-240.
22. Weichen Liu, Jiang Xu, Xiaowen Wu, Yaoyao Ye, Xuan Wang, Wei Zhang, M. Nikdast, and Zhehui Wang. 2011. ANoC traffic suite based on real applications. In Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI). 66-71.
23. Peter Marwedel. 2011. Embedded System Design 2nd Ed., Springer.
24. Aline Mello, Leonel Tedesco, Ney Calazans, and Fernando Moraes. 2005. Virtual channels in networks on chip: Implementation and evaluation on hermes NoC. In Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design (SBCCI). ACM, 178-183.
25. Aline Mello, L. Copello Ost, F. G. Moraes, and Ney Calazans. 2004. Evaluation of routing algorithms on mesh based NoCs. Technical Report, Faculdade de Informatica - PUCRS.
26. B. Nikolic, P. Meumeu Yomsi, and S. M. Petters. 2014. Worst-case communication delay analysis for manycores using a limited migrative model. In Proceedings of the IEEE 20th International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA). 1-10.
27. Luciano Ost et al. 2013. Power-aware dynamic mapping heuristics for NoC-based MPSoCs using a unified model-based approach. ACM Trans. Embed. Comput. Syst. 12, 3 (2013), 75:1-75:22.
28. Luciano Ost, Guilherme Guindani, Leandro Soares Indrusiak, Cezar Reinbrecht, Thiago Raupp, and Fernando Moraes. 2009. A high abstraction, high accuracy power estimation model for networks-onchip. In Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes. ACM, 1-6.
29. Yue Qian, Zhonghai Lu, and Wenhua Dou. 2009. Analysis of worst-case delay bounds for best-effort communication in wormhole networks on chip. In Proceedings of the 3rd ACM/IEEE International Symposium on Networks-on-Chip. IEEE Computer Society, 44-53.
30. Gunar Schirner and Rainer Dömer. 2007. Result-oriented modeling-A novel technique for fast and accurate TLM. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 26, 9 (2007), 1688-1699.
31. Gunar Schirner and Rainer Dömer. 2008. Quantitative analysis of the speed/accuracy trade-off in transaction level modeling. ACM Trans. Embed. Comput. Syst. 8, 1 (2008), 1-29.
32. Zheng Shi and Alan Burns. 2008. Real-time communication analysis for on-chip networks with wormhole switching. In Proceedings of the ACM/IEEE International Symposium on Networks-on-Chip (NOCS). 161-170.
33. Zheng Shi, Alan Burns, and Leandro Soares Indrusiak. 2010. Schedulability analysis for real time on-chip communication with wormhole switching. Int. J. Embed. Real-Time Commun. Syst. 1, 2 (2010), 1-22.
34. H. W. M. van Moll, H. Corporaal, V. Reyes, and M. Boonen. 2009. Fast and accurate protocol specific bus modeling using TLM 2.0. In Proceedings of the Design, Automation & Test in Europe Conference & Exhibition (DATE'09). 316-319.
35. Emmanuel Viaud, François Pêcheux, and Alain Greiner. 2006. An efficient TLM/T modeling and simulation environment based on conservative parallel discrete event principles. In Proceedings of the Conference on Design, Automation and Test in Europe. 94-99.
36. Ke Yu and N. C. Audsley. 2009. A mixed timing system-level embedded software modelling and simulation approach. In Proceedings of the International Conference on Embedded Software and Systems (ICESS). 193-200.