Self-adaptive network on chips

SBCCI 2014: Proceedings of the 27th Symposium on Integrated Circuits and Systems Design

Volumn , Issue , 2014, Pages

  Diguet, Jean Philippe ^a  

^a CNRS   (France)

Author keywords

Network Interface section; NOC; SOC

Indexed keywords

ENERGY EFFICIENCY; INTEGRATED CIRCUIT DESIGN; MICROPROCESSOR CHIPS; SYSTEM-ON-CHIP; TIME DIVISION MULTIPLE ACCESS;

ADAPTIVE NETWORKS; EFFICIENCY AND PERFORMANCE; NOC; RUNTIMES; SOC; UNCERTAIN ENVIRONMENTS;

NETWORK-ON-CHIP;

EID: 84949143527     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2660540.2660992     Document Type: Conference Paper

References (27)

1. N. Beckmann and D. Sanchez. Jigsaw: Scalable software-deffned caches. In 22nd Int. Conf. on Parallel Architectures and Compilation Techniques (PACT), 2013.
2. L. Benini and G. De Micheli. Powering networks on chips. System Synthesis, 2001. Proceedings. The 14th International Symposium on, pages 33-38, 2001.
3. A. Berman and I. Keidar. Low-overhead error detection for networks-on-chip. In IEEE ICCD, Oct 2009.
4. T. Bjerregaard and S. Mahadevan. A survey of research and practices of network-on-chip. ACM Computing Surveys, 38, 2006.
5. C. Bobda, A. Ahmadinia, M. Majer, J. Teich, S. Fekete, and J. van der Veen. DyNoC: A dynamic infrastructure for communication in dynamically reconffgurable devices. In IEEE FPL, pages 153-158, 2005.
6. P. Bogdan, R. Marculescu, S. Jain, and R. Gavila. An optimal control approach to power management for multi-voltage and frequency islands multiprocessor platforms under highly variable workloads. In 6th IEEE/ACM NoCS, may 2012.
7. C. Ciordas, T. Basten, A. Rffadulescu, K. Goossens, and J. V. Meerbergen. An event-based monitoring service for networks on chip. ACM Trans. Des. Autom. Electron. Syst., 10(4), Oct. 2005.
8. R. Dafali, J.-P. Diguet, and J.-C. Creput. Self-adaptive network-on-chip interface. IEEE Embedded Systems Letters, Dec. 2013.
9. W. Dally and B. Towles. Principles and practices of interconnection networks. Morgan Kaufmann, 2004.
10. R. Das, S. Narayanasamy, S. Satpathy, and R. Dreslinski. Catnap: Energy proportional multiple network-on-chip. In ACM/IEEE ISCA, 2013.
11. S. Evain, J.-P. Diguet, and D. Houzet. NoC design ow for TDMA and QoS management in a GALS context. EURASIP Journal on Embedded Systems, 2006.
12. P. Guerrier and A. Greiner. A generic architecture for on-chip packet-switched interconnections. In DATE, 2000.
13. A. Hansson, M. Coenen, and K. Goossens. Undisrupted quality-of-service during reconffguration of multiple applications in networks on chip. In IEEE/ACM Design, Automation and Test in Europe Conf. (DATE), apr. 2007.
14. M. Huebner, M. Ullmann, L. Braun, A. Klausmann, and J. Becker. Scalable application-dependent network on chip adaptivity for dynamical reconffgurable real-time systems. In 14th FPL, Leuven, 2004.
15. J-Ph. Diguet, S. Evain, R. Vaslin, G. Gogniat, and E. Juin. Noc-centric security of reconffgurable soc. In 1st ACM/IEEE Int. Symp. on Networks-on-Chips, Princeton, USA, 2007.
16. J.-J. Lecler and G. Baillieu. Application driven NoC architecture exploration & reffnement for a complex SoC. Design Automation for Embedded Systems Journal, Springer, 2011.
17. A. Leroy, F. Catthoor, D. Verkest, and F. Robert. Spatial division multiplexing: a novel approach for guaranteed throughput on nocs. In DATE, 2006.
18. T. Marescaux, B. Bricke, P. Debacker, V. Nollet, and H. Corporaal. Dynamic time-slot allocation for qos enabled networks on chip. In 3rd Workshop on Embedded Systems for Real-Time Multimedia, 2005.
19. C. Nicopoulos, D. Park, J. Kim, N. Vijaykrishnan, M. Yousif, and C. Das. Vichar: A dynamic virtual channel regulator for network-on-chip routers. In 39th IEEE/ACM MICRO, 2006.
20. V. Nollet, T. Marescaux, P. Avasare, D. Verkest, and J.-Y. Mignolet. Centralized run-time resource management in a network-on-chip containing reconffgurable hardware tiles. In Int. Conf. Design, Automation and Test in Europe (DATE), 2005.
21. V. Nollet, T. Marescaux, and D. Verkest. Operating-system controlled network on chip. In 41st DAC, 2004.
22. T. Pionteck, R. Koch, and C. Albrecht. Applying partial reconffguration to networks-on-chips. In IEEE FPL, 2006.
23. A. Radulescu, J. Dielissen, S. Pestana, O. Gangwal, E. Rijpkema, P. Wielage, and K. Goossens. An effcient on-chip ni offering guaranteed services, shared-memory abstraction, and exible network conffguration. IEEE Trans. on CAD, 24(1), Jan 2005.
24. M.-J. Sepulveda, G. Gogniat, R. Pires, W. Chau, and M. Strum. Security-enhanced 3d communication structure for dynamic 3d-mpsocs protection. In 26th IEEE SBCCI, Curitiba, Brazil, 2013.
25. J. Soumya, A. Sharma, and S. Chattopadhyay. Multi-application network-on-chip design using global mapping and local reconffguration. ACM TRETS, 7(2), June 2014.
26. M. Stensgaard and J. Sparso. ReNoC: A network-on-chip architecture with reconffgurable topology. In 2nd IEEE/ACM NoCS, 2008.
27. D. Wentzlaff, P. Griffn, H. Hoffmann, L. Bao, B. Edwards, C. Ramey, M. Mattina, C.-C. Miao, J. F. Brown III, and A. Agarwal. On-chip inter-connection architecture of the tile processor. In IEEE Micro, 2007.