Data encoding schemes in networks on chip

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 30, Issue 5, 2011, Pages 774-786

  Palesi, Maurizio ^a   Ascia, Giuseppe ^b   Fazzino, Fabrizio ^c   Catania, Vincenzo ^b  

^a KORE UNIVERSITY OF ENNA   (Italy)

^b UNIVERSITY OF CATANIA   (Italy)

^c Icera Inc   (United Kingdom)

Author keywords

Coupling capacitance; data encoding; low power; network on chip (NoC); power analysis

Indexed keywords

COUPLING CAPACITANCE; DATA ENCODING; LOW POWER; NETWORK ON CHIP (NOC); POWER ANALYSIS;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CAPACITANCE; COMPUTER ARCHITECTURE; ELECTRIC LOSSES; ENCODING (SYMBOLS); ENERGY UTILIZATION; MICROPROCESSOR CHIPS; PROGRAMMABLE LOGIC CONTROLLERS; ROUTERS; SERVERS; TELECOMMUNICATION NETWORKS; VLSI CIRCUITS;

NETWORK CODING;

EID: 79955415149     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2010.2098590     Document Type: Article

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