A detailed and flexible cycle-accurate Network-on-Chip simulator

ISPASS 2013 - IEEE International Symposium on Performance Analysis of Systems and Software

Volumn , Issue , 2013, Pages 86-96

  Jiang, Nan ^a   Balfour, James ^b   Becker, Daniel U ^a   Towles, Brian ^c   Dally, William J ^a   Michelogiannakis, George ^d   Kim, John ^e  

^a STANFORD UNIVERSITY   (United States)

^b GOOGLE INC   (United States)

^c D E Shaw   (United States)

^d LAWRENCE BERKELEY NATIONAL LABORATORY   (United States)

^e Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

FAULT TOLERANT COMPUTER SYSTEMS; NETWORK COMPONENTS; ROUTERS; SIMULATORS;

ACCURATE MODELING; BUFFER MANAGEMENT; CONFIGURABLE NETWORKS; CYCLE-ACCURATE SIMULATORS; MODERN MICROPROCESSOR; PERFORMANCE IMPACT; RESEARCH AND DEVELOPMENT; ROUTER MICROARCHITECTURE;

NETWORK-ON-CHIP;

EID: 84881446599     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISPASS.2013.6557149     Document Type: Conference Paper

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