Low overhead predictability enhancement in non-preemptive network-on-chip routers using Priority Forwarded Packet Splitting

2014 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip, ReCoSoC 2014

Volumn , Issue , 2014, Pages

  Sudev, Bharath ^a   Indrusiak, Leandro Soares ^a  

^a UNIVERSITY OF YORK   (United Kingdom)

Author keywords

Network on Chip; Non preemptive Network on Chip; PFS; Predictability; Priority Forwarded Packet Splitting

Indexed keywords

ROUTERS; SERVERS; VLSI CIRCUITS;

HEAD OF LINE BLOCKING; LOW OVERHEAD; LOW PRIORITIES; NON-PREEMPTIVE; PACKET SPLITTING; PFS; PREDICTABILITY; VIRTUAL CHANNELS;

NETWORK-ON-CHIP;

EID: 84905656774     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ReCoSoC.2014.6860691     Document Type: Conference Paper

References (18)

1. W. J. Dally, Virtual-channel flow control, in Proceedings of the 17th annual international symposium on Computer Architecture, New York, NY, USA, 1990, pp. 60-68
2. R. Stefan, A. Molnos, A. Ambrose, and K. Goossens, A TDM NoC supporting QoS, multicast, and fast connection set-up, in Design, Automation Test in Europe Conference Exhibition (DATE), 2012, 2012, pp. 1283-1288
3. L. Thiele and R. Wilhelm, Design for Timing Predictability, Real-Time Systems, vol. 28, no. 2-3, pp. 157-177, Nov. 2004
4. T.-C. Huang, U. Y. Ogras, and R. Marculescu, Virtual Channels Planning for Networks-on-Chip, in 8th International Symposium on Quality Electronic Design, 2007. ISQED, 2007, pp. 879-884
5. B. Sudev and L. S. Indrusiak, PFT-A low overhead predictability enhancement technique for non-preemptive NoCs, in 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC), 2013, pp. 314-317
6. B. Sudev and L. S. Indrusiak, Predictability Enhancement in Non-preemptive NoCs using Selective Packet Splitting. 12th IEEE International Conference on Industrial Informatics (INDIN), Porto Alegre-Brazil, Jul-2014 (Accepted)
7. F. Moraes, N. Calazans, A. Mello, L. Möller, and L. Ost, HERMES: an infrastructure for low area overhead packet-switching networks on chip, Integration, the VLSI Journal, vol. 38, no. 1, pp. 69-93, Oct. 2004
8. K. Goossens, J. Dielissen, and A. Radulescu, AEthereal network on chip: concepts, architectures, and implementations, Design Test of Computers, IEEE, vol. 22, no. 5, pp. 414-421, Oct. 2005
9. R. Dobkin, R. Ginosar, and I. Cidon, QNoC Asynchronous Router with Dynamic Virtual Channel Allocation, in 1st International Symposium on Networks-on-Chip,.2007, 7, p. 218
10. T. Bjerregaard and J. Sparso, A router architecture for connection-oriented service guarantees in the MANGO clockless network-on-chip, in Design, Automation and Test in Europe, 2005. Proceedings, 2005, pp. 1226-1231 Vol. 2
11. S. Park, T. Krishna, C.-H. Chen, B. Daya, A. Chandrakasan, and L.-S. Peh, Approaching the theoretical limits of a mesh NoC with a 16-node chip prototype in 45nm SOI, in 2012 49th ACM/EDAC/IEEE Design Automation Conference (DAC), 2012, pp. 398-405
12. A. Kahng, B. Li, L.-S. Peh, and K. Samadi, ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration, in Design, Automation &Test in Europe Conference &Exhibition, 2009. DATE 09., 2009, pp. 423-428
13. A. Mello, L. Tedesco, N. Calazans, and F. Moraes, Virtual channels in networks on chip: implementation and evaluation on hermes NoC, in Proceedings of the 18th annual symposium on Integrated circuits and system design, New York, NY, USA, 2005, pp. 178-183
14. A. Morgenshtein, A. Kolodny, and R. Ginosar, Link Division Multiplexing (LDM) for Network-on-Chip Links, in 2006 IEEE 24th Convention of Electrical and Electronics Engineers in Israel, 2006, pp. 245-249
15. P. Kundu, On-Die Interconnects for Next Generation CMPs. Proc. Workshop On-and Off-Chip Interconnection Networks for Multicore Systems,, Dec-2006
16. F. Ge, N. Wu, and Y. Wan, A network monitor based dynamic routing scheme for Network on Chip, in Microelectronics Electronics, 2009. PrimeAsia 2009. Asia Pacific Conference on Postgraduate Research in, 2009, pp. 133-136
17. R. Manevich, I. Cidon, A. Kolodny, I. Walter, and S. Wimer, A Cost Effective Centralized Adaptive Routing for Networks-on-Chip, in Digital System Design (DSD), 2011 14th Euromicro Conference on, 2011, pp. 39-46
18. V. Rantala, T. Lehtonen, P. Liljeberg, and J. Plosila, Distributed Traffic Monitoring Methods for Adaptive Network-on-Chip, in NORCHIP, 2008., 2008, pp. 233-236.