Combining sdm-based circuit switching with packet switching in a NoC for real-time applications

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2011, Pages 2505-2508

  Lusala, Angelo Kuti ^a   Legat, Jean Didier ^a  

^a UNIVERSITÉ CATHOLIQUE DE LOUVAIN   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

BEST-EFFORT TRAFFIC; CIRCUIT SWITCHING; CMOS CIRCUITS; COMPLEX DESIGNS; NETWORK ON CHIP; PACKET-SWITCHED; PATH DIVERSITY; REAL-TIME APPLICATION; RESOURCE UTILIZATIONS; SUB-NETWORK; SUBNETWORKS;

CMOS INTEGRATED CIRCUITS; PACKET SWITCHING; SERVERS; SPACE DIVISION MULTIPLE ACCESS; SWITCHING; SWITCHING CIRCUITS; VLSI CIRCUITS;

REAL TIME SYSTEMS;

EID: 79960853955     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2011.5938113     Document Type: Conference Paper

References (7)

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2. A. Kuti Lusala and J-D. Legat, "Combining Circuit and Packet Switching with Bus Architecture in a NoC for Real-Time Applications ", in Proc. of ISCAS 2010, pp. 2880-2883, May 30-June 2, 2010, Paris.
3. E. Bollotin et al, "QNoC: QoS Architecture and Design Proces for Network on Chip", in JSA, Vol. 50 (2-3), pp. 105-128, Feb 2004.
4. A. Leroy et al., "Spatial Division Multiplexing : a Novel Approach for Guaranteed Throughput on NoCs", in Proc. of ISLPED, 2005.
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6. N. E. Jerger et al., "Circuit-Switched Coherence" in computer architecture letters, Vol. 6 (1), pp. 5-8, June 2007.
7. M. Modarressi et al, "A Hybrid Packet-Crcuit Switched On-Chip Network Based on SDM" in Proc. Of DATE 09, pp 566-569, April 2009.