Analyzing CUDA workloads using a detailed GPU simulator

ISPASS 2009 - International Symposium on Performance Analysis of Systems and Software

Volumn , Issue , 2009, Pages 163-174

  Bakhoda, Ali ^a   Yuan, George L ^a   Fung, Wilson W L ^a   Wong, Henry ^a   Aamodt, T M ^a  

^a UNIVERSITY OF BRITISH COLUMBIA   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

BISECTION BANDWIDTH; COMPUTING POWER; DATA-LEVEL PARALLELISM; FLEXIBLE PROGRAMMING MODEL; GRAPHIC PROCESSING UNITS; HIGH-END GRAPHICS; INSTRUCTION SET; INTERCONNECT TOPOLOGY; MANY-CORE; MEMORY CONTROLLER; MEMORY SYSTEMS; MICRO ARCHITECTURES; MICRO-ARCHITECTURE DESIGN; MULTITHREADED; NON-TRIVIAL; ON CHIPS; ORDERS OF MAGNITUDE; PEAK PERFORMANCE; PERFORMANCE IMPACT; PERFORMANCE IMPROVEMENTS; PERFORMANCE SIMULATOR; PROGRAMMING MODELS; THREAD LEVEL PARALLELISM; WORK-LOAD DISTRIBUTION;

COMPUTER GRAPHICS EQUIPMENT; FLOCCULATION; MACHINE DESIGN; PROGRAM PROCESSORS; SIMULATORS;

CACHE MEMORY;

EID: 70349169075     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISPASS.2009.4919648     Document Type: Conference Paper

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