SurfNoC: A low latency and provably non-interfering approach to secure networks-on-chip

Proceedings - International Symposium on Computer Architecture

Volumn , Issue , 2013, Pages 583-594

  Wassel, Hassan M G ^a   Gao, Ying ^a   Oberg, Jason K ^b   Huffmire, Ted ^c   Kastner, Ryan ^b   Chong, Frederic T ^a   Sherwood, Timothy ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c NAVAL POSTGRADUATE SCHOOL   (United States)

Author keywords

High Assurance Systems; Networks on chip; Non interference

Indexed keywords

HIGH ASSURANCE SYSTEMS; INFORMATION FLOW ANALYSIS; MULTI-CORE PROCESSOR; NETWORKS ON CHIPS; NON INTERFERENCE; ROUTER MICROARCHITECTURE; SCHEDULING POLICIES; TEMPORAL PARTITIONING;

BIOMEDICAL EQUIPMENT; COMPUTER ARCHITECTURE; MULTIPLEXING;

INTERFERENCE SUPPRESSION;

EID: 84881183208     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2485922.2485972     Document Type: Conference Paper

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