Performance modeling of low-k/Cu interconnects for 32-nm-node and beyond

IEEE Transactions on Electron Devices

Volumn 56, Issue 9, 2009, Pages 1852-1861

  Tada, Munehiro ^a   Inoue, Naoya ^b   Hayashi, Yoshihiro ^b  

^a NEC CORPORATION   (Japan)

^b RENESAS TECHNOLOGY CORP   (Japan)

Author keywords

Delay; Low k Cu interconnects; Power consumption; Scaling

Indexed keywords

ACTIVE POWER; DELAY; INTERCONNECT PERFORMANCE; INTERCONNECT RELIABILITY; INTERCONNECT RESISTANCE; K-VALUE; LINE RESISTIVITY; LOW-K FILMS; LOW-K/CU INTERCONNECTS; PER UNIT; PERFORMANCE MODELING; POWER CONSUMPTION; RESISTANCE CAPACITANCE; SCALING; SMALL-SIZE EFFECTS; TECHNOLOGY NODES; ULTRALARGE SCALE INTEGRATION;

ELECTRIC POWER UTILIZATION; ULSI CIRCUITS;

CAPACITANCE;

EID: 69549102947     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2009.2026519     Document Type: Article

References (66)

1. K. C. Saraswat and F. Mohammadi, "Effects of interconnection scaling on time delay of VLSI circuits," IEEE Trans. Electron Devices, vol. ED-29, no. 4, pp. 645-650, Apr. 1982.
2. M. T. Bohr, "Interconnect scaling - The real limiter to high performance," in Proc. IEDM Tech. Dig., 1995, pp. 241-242.
3. Y. Hayashi, "Impacts of low-k film on sub-100 nm-node, ULSI devices," in Proc. IEEE Int. Interconnect Technol. Conf., 2002, pp. 312-314.
4. M. Tada, H. Ohtake, J. Kawahara, and Y. Hayashi, "Effect of material interfaces in Cu/low-K damascene interconnects on their performance and reliability," IEEE Trans. Electron Devices, vol. 51, no. 11, pp. 1867-1876, Nov. 2004.
5. D. Edelstein, J. Heidenreich, R. Goldblatt, W. Cote, C. Uzoh, N. Lustig, P. Roper, T. McDevitt, W. Motsiff, A. Simon, J. D. Dukovic, R. Wachnik, H. Rathore, R. Schulz, L. Su, and J. Slattery, "Full copper wiring in a sub-0.25 μm CMOS ULSI technology," in Proc. IEDM Tech. Dig., 1997, pp. 773-776.
6. H. Ohtake, M. Tagami, M. Tada, M. Ueki, S. Saito, and Y. Hayashi, "Robust Cu dual damascene interconnects with porous SiOCH films fabricated by low-damage multi-hard-mask etching technology," IEEE Trans. Semicond. Manuf., vol. 19, no. 4, pp. 455-464, Nov. 2006.
7. M. A. Hussein and J. He, "Materials impact in interconnect process technology and reliability," IEEE Trans. Semicond. Manuf., vol. 18, no. 1, pp. 69-85, Feb. 2005.
8. K. Fuchs, "The conductivity of thin metallic films according to the electron theory of metals," Cambridge Philos. Soc., vol. 34, no. 1, pp. 100-108, 1938.
9. E. H. Sondheimer, "The mean free path of electrons in materials," Adv. Phys., vol. 1, no. 1, pp. 1-42, Jan. 1952.
10. J. A. Davis, R. Venkatesan, A. Kaloyeros, M. Beylansky, S. J. Souri, K. Banerjee, K. C. Saraswat, A. Rahman, R. Reif, and J. D. Meindl, "Interconnect limits on gigascale integration (GSI) in the 21st century," Proc. IEEE, vol. 89, no. 3, pp. 305-324, Mar. 2001.
11. M. Tada, M. Abe, N. Furutake, F. Ito, T. Tonegawa, M. Sekine, and Y. Hayashi, "Reliability improvement of 65 nm-node, Cu dual damascene interconnects by impurity-doping and interface-strengthening," IEEE Trans. Electron Devices, vol. 54, no. 8, pp. 1867-1877, Aug. 2007.
12. M. Ueki, M. Hiroi, N. Ikarashi, T. Onodera, N. Furutake, N. Inoue, and Y. Hayashi, "Effects of Ti addition on via reliability in Cu dual damascene interconnects," IEEE Trans. Electron Devices, vol. 49, no. 1, pp. 89-95, Jan. 2002.
13. K.-D. Lee and P. S. Ho, "Statistical study for electromigration reliability in dual-damascene Cu interconnects," IEEE Trans. Device Mater. Rel., vol. 4, no. 2, pp. 237-245, Jun. 2004.
14. E. T. Ogawa, J. W. McPherson, J. A. Rosal, K. J. Dickerson, T.-C. Chiu, L. Y. Tsung, M. K. Jain, T. D. Bonifiled, J. C. Ondrusek, andW. R. McKee, "Stress-induced voiding under vias connected to wide Cu metal leads," in Proc. IEEE Int. Reliab. Phys. Symp., 2002, pp. 312-321.
15. S. Yokogawa, K. Kikuta, H. Tsuchiya, T. Takewaki, M. Suzuki, H. Toyoshima, Y. Kakuhara, N. Kawahara, T. Usami, K. Ohto, K. Fujii, T. Tsuchiya, K. Arita, K. Motoyama, M. Tohara, T. Taiji, T. Kurokawa, andM. Sekine, "Tradeoff characteristics between resistivity and reliability for scaled-down Cu-based interconnects," IEEE Trans. Electron Devices, vol. 55, no. 1, pp. 350-357, Jan. 2008.
16. M. Tada, T. Tamura, F. Itoh, H. Ohtake, M. Narihiro, M. Tagami, M. Ueki, K. Hijioka, M. Abe, N. Inoue, T. Takeuchi, S. Saito, T. Onodera, N. Furutake, K. Arai, M. Sekine, M. Suzuki, and Y. Hayashi, "Robust porous SiOCH/Cu interconnects with ultrathin sidewall protection liners," IEEE Trans. Electron Devices, vol. 53, no. 5, pp. 1169-1179, May 2006.
17. N. Inoue, N. Furutake, F. Ito, H. Yamamoto, T. Takeuchi, and Y. Hayashi, "Impact of barrier metal sputtering on physical and chemical damages in low-k SiOCH films with various hydrocarbon content," Jpn. J. Appl. Phys., vol. 47, no. 4, pp. 1468-1472, Apr. 2008.
18. Z. Tökeia, Y.-L. Lia, and G. P. Beyer, "Reliability challenges for copper low-k dielectrics and copper diffusion barriers," Microelectron. Reliab., vol. 45, no. 9-11, pp. 1436-1442, Sep.-Nov. 2005.
19. V. N. Hoang, G. Doornbos, J. Michelon, A. Kumar, A. Nackaerts, and P. Christie, "Balancing resistance and capacitance of signal interconnects for power saving," in Proc. IEEE Int. Interconnect Technol. Conf. 2007, pp. 126-128.
20. M. Ueki, M. Narihiro, H. Ohtake, M. Tagami, M. Tada, F. Ito, Y. Harada, M. Abe, N. Inoue, K. Arai, T. Takeuchi, S. Saito, T. Onodera, N. Furutake, M. Hiroi, M. Sekine, and Y. Hayashi, "Highly reliable, 65 nm-node Cu dual damascene interconnects with full porous-SiOCH (k = 2.5) films for low-power ASICs," in Proc. VLSI Symp. Tech. Dig. 2004, pp. 60-61.
21. M. Tagami, H. Ohtake, M. Tada, M. Ueki, F. Ito, T. Taiji, Y. Kasama, T. Iwamoto, H. Wakabayashi, T. Fukai, K. Arai, S. Saito, H. Yamamoto, M. Abe, M. Narihiro, N. Furutake, T. Onodera, T. Takeuchi, Y. Tsuchiya, N. Oda, M. Sekine, M. Hane, and Y. Hayashi, "High-performance Cuinterconnects with novel seamless low-k SiOCH stacks (SEALS) featured by compositional modulation process for 45 nm-node ULSI devices," in Proc. VLSI Symp. Tech. Dig., 2006, pp. 134-135.
22. M. Tada, H. Yamamoto, F. Ito, M. Narihiro, M. Ueki, N. Inoue, M. Abe, S. Saito, T. Takeuchi, N. Furutake, T. Onodera, J. Kawahara, K. Arai, Y. Kasama, T. Taiji, M. Tohara, M. Sekine, and Y. Hayashi, "Plasma copolymerization technology with molecular-level structure tightening in "In-situ" SiOCH stacks for 32 nm-node Cu interconnects," in Proc. IEDM Tech. Dig., 2006, pp. 351-354.
23. K. Hijioka, F. Ito, M. Tagami, H. Ohtake, Y. Harada, T. Takeuchi, S. Saitoh, and Y. Hayashi, "Mechanical property control of low-k dielectrics for diminishing chemical mechanical polishing (CMP)-related defects in Cu-damascene interconnects," Jpn. J. Appl. Phys., vol. 43, no. 4B, pp. 1807-1812, 2004.
24. N. Inoue, M. Tagami, F. Ito, H. Yamamoto, T. Takeuchi, S. Saito, N. Furutake, M. Ueki, M. Tada, T. Suzuki, and Y. Hayashi, "45 nm-node interconnects with porous SiOCH-stacks, tolerant of low-cost packaging applications," in Proc. IEEE Int. Interconnect Technol. Conf., 2007, pp. 181-183.
25. F. Ito, T. Takeuchi, and Y. Hayashi, "Improvement of mechanical properties of porous SiOCH films by post-cure treatment," in Proc. Adv. Metallization Conf., 2005, pp. 10-11.
26. M. Tada, H. Yamamoto, T. Takeuchi, N. Furutake, F. Ito, and Y. Hayashi, "Effects of side-chains on the structural and electrical properties of plasma-polymerized SiOCH thin film," J. Electrochem. Soc., vol. 154, no. 7, pp. D354-D361, 2007.
27. Y. Hayashi, H. Ohtake, J. Kawahara, M. Tada, S. Saito, N. Inoue, F. Ito, M. Tagami, M. Ueki, N. Furutake, T. Takeuchi, H. Yamamoto, and M. Abe, "Comprehensive chemistry designs in porous SiOCH film stacks and plasma etching gases for damageless Cu interconnects in advanced ULSI devices," IEEE Trans. Semicond. Manuf., vol. 21, no. 3, pp. 469-480, Aug. 2008.
28. eff = 2.75) with continuous SiOCH stack incorporating a low-k barrier cap (k = 3.1)," in Proc. IEDM Tech. Dig., 2007, pp. 973-976.
29. Y. Travaly, B. Mandeep, L. Carbonell, Z. Tökei, J. V. Olmen, F. Iacopi, M. V. Hove,M. Stucchi, and K. Maex, "On a more accurate assessment of scaled copper/low-k interconnects performance," IEEE Trans. Semicond. Manuf., vol. 20, no. 3, pp. 333-340, Aug. 2007.
30. J. A. Davis, V. De, and J. D. Meindl, "A stochastic wire-length distribution for gigascale integration (GSI) - Part 1: Derivation and validation," IEEE Trans. Electron Devices, vol. 45, no. 3, pp. 580-589, Mar. 1998.
31. J. A. Davis, V. De, and J. D. Meindl, "A stochastic wire-length distribution for gigascale integration (GSI) - Part 2: Applications to clock frequency, power dissipation, and chip size estimation," IEEE Trans. Electron Devices, vol. 45, no. 3, pp. 590-597, Mar. 1998.
32. J. D. Meindl, R. Venkatesan, J. A. Davis, J. Joyner, A. Naeemi, P. Zarkesh-Ha, M. Bakir, T. Mule, P. A. Kohl, and K. P. Martin, "Interconnecting device opportunities for gigascale integration (GSI)," in Proc. IEDM Tech. Dig., 2001, pp. 525-528.
33. G. Chen and E. G. Friedman, "Low-power repeaters driving RC and RLC interconnects with delay and bandwidth constraints," IEEE Trans. Electron Devices, vol. 14, no. 2, pp. 161-172, Feb. 2006.
34. P. Kapur, P. Mc. Vittie, and K. C. Saraswat, "Technology and reliability constrained future copper interconnects - Part 1: Resistance modeling," IEEE Trans. Electron Devices, vol. 49, no. 4, pp. 590-597, Apr. 2002.
35. P. Kapur, G. Chandra, P. McVittie, and K. C. Saraswat, "Technology and reliability constrained future copper interconnects - Part 2: Performance implications," IEEE Trans. Electron Devices, vol. 49, no. 4, pp. 590-597, Apr. 2002.
36. 2PAL) model," IEEE Trans. Electron Devices vol. 48, no. 2, pp. 239-251, Feb. 2001.
37. A. F. Mayadas and M. Shatzkes, "Electrical-resistivity model for polycrystalline films: The case of arbitrary reflection at external surfaces," Phys. Rev. B, Condens. Matter, vol. 1, no. 4, pp. 1382-1389, Feb. 1970.
38. G. Steinlesberger,M. Engelhardt, G. Schindler,W. Steinhögl,M. Traving, W. Hönlein, and E. Bertagnolli, "Impact of annealing on the resistivity of ultrafine Cu damascene interconnects," in Proc. Mater. Res. Soc. Symp., 2003, vol. 766, pp. 379-384.
39. W. Steinhögl, G. Schindler, G. Steinlesberger, and M. Engelhardt, "Size-dependent resistivity of metallic wire in the microscopic range," Phys. Rev. B, Condens. Matter, vol. 66, no. 7, p. 075 414-1, Aug. 2002.
40. T. Sun, B. Yao, A. Warren, V. Kumar, K. Barmak, and K. R. Coffey, "Resistivity size effect in encapsulated Cu thin film," in Proc. IEEE Int. Interconnect Technol. Conf., 2008, pp. 141-143.
41. J. V. Olmen, S. List, Z. Tokei, L. Carbonell, S. H. Brongersma, H. Volders, E. Kunnen, N. Heylen, I. Ciofi, A. Khandelwal, J. Gelatos, T. Mandrekar, and P. Boelen, "Cu resistivity scaling limits for 20 nm copper damascene lines," in Proc. IEEE Int. Interconnect Technol. Conf., 2008, pp. 49-51.
42. K. Hinode, Y. Hanaoka, K. Takeda, and S. Kondo, "Resistivity increase in ultrafine-line copper conductor for ULSIs," Jpn. J. Appl. Phys. vol. 40, no. 10B, pp. L1 097-L1 099, Oct. 2001.
43. S. Tashiro, K. Khoo, T. Nagano, J. Onuki, Y. Chonan, H. Akahoshi, T. Tobita, M. Chiba, K. Ishikawa, and N. Ishikawa, "The development of an innovative process of large grained and low resistivity Cu wires for less than hp 45 nmULSI," in Proc. IEEE Int. Interconnect Technol. Conf., 2007, pp. 46-48.
44. S. M. Rossnagel and T. S. Kuan, "Alteration of Cu conductivity in the size effect regime," J. Vac. Sci. Technol. B, Microelectron. Process. Phenom., vol. 22, no. 1, pp. 240-247, Jan./Feb. 2004.
45. M. Tada, H. Ohtake, F. Ito, M. Narihiro, T. Taiji, Y. Kasama, T. Takeuchi, K. Arai, N. Furutake, N. Oda, M. Sekine, and Y. Hayashi, "Feasibility study of 45-nm-node scaled-down Cu interconnects with molecular-porestacking (MPS) SiOCH films," IEEE Trans. Electron Devices, vol. 54, no. 4, pp. 797-806, Apr. 2007.
46. C.-C. Yang, T. Spooner, S. Ponoth, K. Chanda, A. Simon, C. Lavoie, M. Lane, C.-K. Hu, E. Liniger, L. Gignac, T. Shaw, S. Cohen, F. McFeely, and D. Edelstein, "Physical, electrical, and reliability characterization of Ru for Cu interconnects," in Proc. IEEE Int. Interconnect Technol. Conf., 2006, pp. 187-190.
47. M. Abe, M. Ueki, M. Tada, T. Onodera, N. Furutake, K. Shimura, S. Saito, and Y. Hayashi, "Highly-oriented PVD Ruthenium liner for low-resistance direct-plated Cu interconnects," in Proc. IEEE Int. Interconnect Technol. Conf., 2007, pp. 4-6.
48. M. Tagami, N. Furutake, S. Saito, and Y. Hayashi, "Highly-reliable low-resistance Cu interconnects with PVD-Ru/Ti barrier metal toward automotive LSIs," in Proc. IEEE Int. Interconnect Technol. Conf., 2008, pp. 205-207.
49. V. Ligatchev, T. K. S.Wong, B. Liu, and Rusli, "Atomic structure and defect densities in low dielectric constant carbon doped hydrogenated silicon oxide films, deposited by plasma-enhanced chemical vapor deposition," J. Appl. Phys., vol. 92, no. 8, pp. 4605-4611, Oct. 2002.
50. A. Grill and V. Patel, "Low dielectric constant films prepared by plasma-enhanced chemical vapor deposition from tetramethylsilane," J. Appl. Phys., vol. 85, no. 6, pp. 3314-3318, Mar. 1999.
51. L. M. Han, J. Pan, S. Chen, N. Balasubramanian, J. Shi, L. S. Wong, and P. D. Foo, "Characterization of carbon-doped SiO2 low k thin films preparation by plasma-enhanced chemical vapor deposition from tetramethylsilane," J. Electrochem. Soc., vol. 148, pp. 148-153, 2001.
52. Y. H. Kim, S. K. Lee, and H. J. Kim, "Low-k Si-O-C-H composite films prepared by plasma-enhanced chemical vapor deposition using bistrimethylsilylmethane precursor," J. Vac. Sci. Technol. A, Vac. Surf. Films, vol. 18, no. 4, pp. 1216-1219, Jul. 2000.
53. M. R. Wang, Rusli, J. L. Xie, N. Babu, C. Y. Li, and K. Rakesh, "Study of oxygen influences on carbon doped silicon oxide low k thin films deposited by plasma enhanced chemical vapor deposition," J. Appl. Phys., vol. 96, no. 1, pp. 829-834, Jul. 2004.
54. D. Shamiryan, K. Weidner, W. D. Gray, M. R. Baklanov, S. Vanhaelemeersch, and K. Maex, "Comparative study of PECVD SiOCH low-k films obtained at different deposition conditions," Microelectron. Eng., vol. 64, no. 1, pp. 361-366, Oct. 2002.
55. R. D. Goldblatt, B. Agarwala, M. B. Anand, E. P. Barth, G. A. Biery, Z. G. Chen, S. Cohen, J. B. Connolly, A. Cowley, T. Dalton, S. K. Das, C. R. Davis, A. Deutsch, C. DeWan, D. C. Edelstein, P. A. Emmi, C. G. Faltermeier, J. A. Fitzsimmons, J. Hedrick, J. E. Heidenreich, C. K. Hu, J. P. Humme1, P. Jones, E. Kaltalioglu, B. E. Kastenmeier, M. Krishnan, W. F. Landers, E. Liniger, J. Liu, N. E. Lustig, S. Malhotra, D. K. Manger, V. McGahay, R. Mih, H. A. Nye, S. Purushothaman, H. A. Rathore, S. C. Seo, T. M. Shaw, A. H. Simon, T. A. Spooner, M. Stetter, R. A. Wachnik, and J. G. Ryan, "A high performance 0.13 μm copper BEOL technology with low-k dielectric," in Proc. IEEE Int. Interconnect Technol. Conf., 1999, pp. 261-263.
56. O. Demolliens, P. Bermyer, Y.Morand, C. Tabone, A. Roman, M. Cochet, M. Assous, H. Feldis, R. Blanc, E. Tabouret, D. Louis, C. Arvet, E. Lajoinie, Y. Gobil, G. Passernard, F. Jourdan, M. Moussavi, M. Cordeau, T. Morel, T. Mourier, L. Ulmer, E. Sicurani, F. Tardif, A. Beverina, Y. Trouillet, and D. Renaud, "Copper-SilK integration in a 0.18 μm double level metal interconnect," in Proc. IEEE Int. Interconnect Technol. Conf., 1999, pp. 198-199.
57. N. Oda, S. Ito, T. Takewaki, H. Kunishima, N. Hironaga, I. Honma, H. Namba, S. Yokogawa, T. Goto, T. Usami, K. Ohto, A. Kubo, H. Aoki, M. Suzuki, Y. Yamamoto, S. Watanabe, T. Takeda, K. Yamada, M. Kosaka, and T. Horiuchi, "A robust embedded ladder-oxide/Cu multilevel interconnect technology for 0.13-μm CMOS generation," in Proc. VLSI Symp. Tech. Dig., 2002, pp. 34-35.
58. M. Tada, Y. Harada, K. Hijioka, H. Ohtake, T. Takeuchi, S. Saito, T. Onodera, M. Hiroi, N. Furutake, and Y. Hayashi, "Cu dual damascene interconnects in porous organosilica film with organic hard-mask and etch-stop layers for 70 nm-node ULSIs," in Proc. IEEE Int. Interconnect Technol. Conf., 2002, pp. 12-14.
59. M. Ueki, M. Tagami, F. Ito, I. Kume, H. Yamamoto, J. Kawahara, N. Inoue, K. Hijioka, T. Takeuchi, S. Saito, T. Onodera, N. Furutake, N. Okada, and Y. Hayashi, "High performance Cu interconnects with damage-less full molecular-pore-stack (MPS) SiOCH for 32 nm-node LSIs and beyond," in Proc. IEDM Tech. Dig., 2008, pp. 619-622.
60. S. Im, N. Srivastave, K. Banerjee, and K. E. Goodson, "Scaling analysis of multilevel interconnect temperature for high-performance ICs," IEEE Trans. Electron Devices, vol. 52, no. 12, pp. 2710-2719, Dec. 2005.
61. [Online]. Available: http://www.itrs.net/
62. J. Kawahara, M. Ueki, M. Tagami, K. Yako, H. Yamamoto, F. Ito, H. Nagase, S. Saito, N. Furutake, T. Onodera, T. Takeuchi, H. Nakamura, K. Arita, K. Motoyama, E. Nakazawa, K. Fujii, M. Sekine, N. Okada, and Y. Hayashi, "A new direct low-k/Cu dual damascene (DD) contact lines for low-loss (LL) CMOS device platforms," in Proc. VLSI Symp. Tech. Dig. 2008, pp. 106-107.
63. J. Kawahara, K. Hijioka, I. Kume, H. Nagase, A. Tanabe, M. Ueki, H. Yamamoto, F. Ito, N. Inoue, M. Tagami, N. Furutake, T. Onodera, S. Saito, T. Takeuchi, T. Fukai, M. Asada, K. Arita, K. Motoyama, A. Nakajima, E. Nakazawa, R. Kitao, K. Fujii, M. Sekine, M. Ikeda, and Y. Hayashi, "RF performance boosting for 40 nm-node CMOS device by low-k/Cu dual damascene contact," in Proc. IEDM Tech. Dig., 2008, pp. 611-614.
64. A. Cros, M. O. Aboelfotoh, and K. N. Tu, "Formation, oxidation, electronic, and electrical properties of copper silicides," J. Appl. Phys., vol. 67, no. 7, pp. 3328-3336, Apr. 1990.
65. K. Banerjee and A. Mehrotra, "A power-optimal repeater insertion methodology for global interconnects in nanometer designs," IEEE Trans. Electron Devices, vol. 49, no. 11, pp. 2001-2007, Nov. 2002.
66. M. Tada, N. Inoue, J. Kawahara, H. Yamamoto, F. Ito, T. Fukai, M. Ueki, S. Miyake, T. Takeuchi, S. Saito, M. Tagami, N. Furutake, K. Hijioka, O. Yuzawa, T. Ito, Y. Shibue, T. Senou, R. Ikeda, N. Okada, and Y. Hayashi, "Porous low-k impact on performance of advanced LSI devices with GHz operation," Jpn. J. Appl. Phys., vol. 48, p. 04C 301, 2009.