High performance Cu interconnects with damage-less full molecular-pore-stack (MPS) SiOCH for 32nm-node LSIs and beyond

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2008, Pages

  Ueki, M ^a   Tagami, M ^a   Ito, F ^a   Kume, I ^a   Yamamoto, H ^a   Kawahara, J ^a   Inoue, N ^a   Hijioka, K ^a   Takeuchi, T ^a   Saito, S ^a   Onodera, T ^a   Furutake, N ^a   Okada, N ^b   Hayashi, Y ^a  

^a LSI Fundamental Research Lab   (Japan)

^b RENESAS TECHNOLOGY CORP   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CU INTERCONNECT; CU-INTERCONNECTS; DEFECT GENERATIONS; DIRECT CMP; HARD MASKS; K VALUES; LAYER CAPACITANCES; LOW FRICTIONS; PLASMA PROCESS; PLASMA TREATMENTS;

CAPACITANCE; CHEMICAL MODIFICATION; ELECTRON DEVICES; HELIUM; LSI CIRCUITS; OPTICAL INTERCONNECTS; PLASMA APPLICATIONS; SURFACE TREATMENT;

MAGNETOPLASMA;

EID: 64549135353     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2008.4796767     Document Type: Conference Paper

References (7)

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6. M. Ueki, et al., IEEE IEDM, p.973 (2007)
7. Y. Hayashi et al., IEEE Trans. SMT, Vol.21, No. 3, p469, (2008)